256 lines
12 KiB
ReStructuredText
256 lines
12 KiB
ReStructuredText
.. _rdt_configuration:
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Enable RDT Configuration
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########################
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On x86 platforms that support Intel Resource Director Technology (RDT)
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allocation features such as Cache Allocation Technology (CAT) and Memory
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Bandwidth Allocation (MBA), the ACRN hypervisor can be used to limit regular
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VMs that may be over-utilizing common resources such as cache and memory
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bandwidth relative to their priorities so that the performance of other
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higher priority VMs (such as RTVMs) is not impacted.
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Using RDT includes three steps:
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1. Detect and enumerate RDT allocation capabilities on supported
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resources such as cache and memory bandwidth.
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#. Set up resource mask array MSRs (model-specific registers) for each
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CLOS (class of service, which is a resource allocation), basically to
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limit or allow access to resource usage.
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#. Select the CLOS for the CPU associated with the VM that will apply
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the resource mask on the CP.
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Steps #2 and #3 configure RDT resources for a VM and can be done in two ways:
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* Using an HV debug shell (See `Tuning RDT resources in HV debug shell`_)
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* Using a VM configuration (See `Configure RDT for VM using VM Configuration`_)
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The following sections discuss how to detect, enumerate capabilities, and
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configure RDT resources for VMs in the ACRN hypervisor.
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For further details, refer to the ACRN RDT high-level design
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:ref:`hv_rdt` and `Intel 64 and IA-32 Architectures Software Developer's
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Manual, (Section 17.19 Intel Resource Director Technology Allocation Features)
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<https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide>`_
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.. _rdt_detection_capabilities:
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RDT Detection and Resource Capabilities
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***************************************
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From the ACRN HV debug shell, use ``cpuid`` to detect and identify the
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resource capabilities. Use the platform's serial port for the HV shell.
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Check if the platform supports RDT with ``cpuid``. First, run
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``cpuid 0x7 0x0``; the return value EBX [bit 15] is set to 1 if the
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platform supports RDT. Next, run ``cpuid 0x10 0x0`` and check the EBX
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[3-1] bits. EBX [bit 1] indicates that L3 CAT is supported. EBX [bit 2]
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indicates that L2 CAT is supported. EBX [bit 3] indicates that MBA is
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supported. To query the capabilities of the supported resources, use the
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bit position as a subleaf index. For example, run ``cpuid 0x10 0x2`` to
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query the L2 CAT capability.
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.. code-block:: none
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ACRN:\>cpuid 0x7 0x0
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cpuid leaf: 0x7, subleaf: 0x0, 0x0:0xd39ffffb:0x00000818:0xbc000400
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L3/L2 bit encoding:
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* EAX [bit 4:0] reports the length of the cache mask minus one. For
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example, a value 0xa means the cache mask is 0x7ff.
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* EBX [bit 31:0] reports a bit mask. Each set bit indicates the
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corresponding unit of the cache allocation that can be used by other
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entities in the platform (e.g. integrated graphics engine).
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* ECX [bit 2] if set, indicates that cache Code and Data Prioritization
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Technology is supported.
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* EDX [bit 15:0] reports the maximum CLOS supported for the resource
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minus one. For example, a value of 0xf means the max CLOS supported
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is 0x10.
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.. code-block:: none
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ACRN:\>cpuid 0x10 0x0
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cpuid leaf: 0x10, subleaf: 0x0, 0x0:0xa:0x0:0x0
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ACRN:\>cpuid 0x10 **0x1**
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cpuid leaf: 0x10, subleaf: 0x1, 0xa:0x600:0x4:0xf
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MBA bit encoding:
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* EAX [bit 11:0] reports the maximum MBA throttling value minus one. For example, a value 0x59 means the max delay value is 0x60.
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* EBX [bit 31:0] reserved.
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* ECX [bit 2] reports whether the response of the delay values is linear.
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* EDX [bit 15:0] reports the maximum CLOS supported for the resource minus one. For example, a value of 0x7 means the max CLOS supported is 0x8.
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.. code-block:: none
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ACRN:\>cpuid 0x10 0x0
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cpuid leaf: 0x10, subleaf: 0x0, 0x0:0xa:0x0:0x0
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ACRN:\>cpuid 0x10 **0x3**
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cpuid leaf: 0x10, subleaf: 0x3, 0x59:0x0:0x4:0x7
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.. note::
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ACRN takes the lowest common CLOS max value between the supported
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resources as maximum supported CLOS ID. For example, if max CLOS
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supported by L3 is 16 and MBA is 8, ACRN programs MAX_PLATFORM_CLOS_NUM
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to 8. ACRN recommends having consistent capabilities across all RDT
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resources by using a common subset CLOS. This is done in order to minimize
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misconfiguration errors.
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Tuning RDT Resources in HV Debug Shell
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**************************************
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This section explains how to configure the RDT resources from the HV debug
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shell.
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#. Check the pCPU IDs of each VM; the ``vcpu_list`` below shows that VM0 is
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running on pCPU0, and VM1 is running on pCPU1:
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.. code-block:: none
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ACRN:\>vcpu_list
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VM ID pCPU ID VCPU ID VCPU ROLE VCPU STATE
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===== ======= ======= ========= ==========
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0 0 0 PRIMARY Running
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1 1 0 PRIMARY Running
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#. Set the resource mask array MSRs for each CLOS with a ``wrmsr <reg_num> <value>``.
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For example, if you want to restrict VM1 to use the
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lower 4 ways of LLC cache and you want to allocate the upper 7 ways of
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LLC to access to VM0, you must first assign a CLOS for each VM (e.g. VM0
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is assigned CLOS0 and VM1 CLOS1). Next, resource mask the MSR that
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corresponds to the CLOS0. In our example, IA32_L3_MASK_BASE + 0 is
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programmed to 0x7f0. Finally, resource mask the MSR that corresponds to
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CLOS1. In our example, IA32_L3_MASK_BASE + 1 is set to 0xf.
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.. code-block:: none
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ACRN:\>wrmsr -p1 0xc90 0x7f0
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ACRN:\>wrmsr -p1 0xc91 0xf
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#. Assign CLOS1 to pCPU1 by programming the MSR IA32_PQR_ASSOC [bit 63:32]
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(0xc8f) to 0x100000000 to use CLOS1 and assign CLOS0 to pCPU 0 by
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programming MSR IA32_PQR_ASSOC [bit 63:32] to 0x0. Note that
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IA32_PQR_ASSOC is per LP MSR and CLOS must be programmed on each LP.
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.. code-block:: none
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ACRN:\>wrmsr -p0 0xc8f 0x000000000 (this is default and can be skipped)
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ACRN:\>wrmsr -p1 0xc8f 0x100000000
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.. _rdt_vm_configuration:
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Configure RDT for VM Using VM Configuration
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*******************************************
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#. RDT hardware feature is enabled by default on supported platforms. This
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information can be found using an offline tool that generates a
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platform-specific XML file that helps ACRN identify RDT-supported
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platforms. RDT on ACRN is enabled by configuring the ``FEATURES``
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sub-section of the scenario XML file as in the below example. For
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details on building ACRN with a scenario, refer to :ref:`build-with-acrn-scenario`.
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.. code-block:: none
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:emphasize-lines: 6
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<FEATURES>
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<RELOC desc="Enable hypervisor relocation">y</RELOC>
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<SCHEDULER desc="The CPU scheduler to be used by the hypervisor.">SCHED_BVT</SCHEDULER>
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<MULTIBOOT2 desc="Support boot ACRN from multiboot2 protocol.">y</MULTIBOOT2>
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<RDT desc="Intel RDT (Resource Director Technology).">
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<RDT_ENABLED desc="Enable RDT">*y*</RDT_ENABLED>
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<CDP_ENABLED desc="CDP (Code and Data Prioritization). CDP is an extension of CAT.">n</CDP_ENABLED>
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<CLOS_MASK desc="Cache Capacity Bitmask"></CLOS_MASK>
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<MBA_DELAY desc="Memory Bandwidth Allocation delay value"></MBA_DELAY>
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</RDT>
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#. Once RDT is enabled in the scenario XML file, the next step is to program
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the desired cache mask or/and the MBA delay value as needed in the
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scenario file. Each cache mask or MBA delay configuration corresponds
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to a CLOS ID. For example, if the maximum supported CLOS ID is 4, then 4
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cache mask settings needs to be in place where each setting corresponds
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to a CLOS ID starting from 0. To set the cache masks for 4 CLOS ID and
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use default delay value for MBA, it can be done as shown in the example below.
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.. code-block:: none
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:emphasize-lines: 8,9,10,11,12
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<FEATURES>
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<RELOC desc="Enable hypervisor relocation">y</RELOC>
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<SCHEDULER desc="The CPU scheduler to be used by the hypervisor.">SCHED_BVT</SCHEDULER>
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<MULTIBOOT2 desc="Support boot ACRN from multiboot2 protocol.">y</MULTIBOOT2>
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<RDT desc="Intel RDT (Resource Director Technology).">
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<RDT_ENABLED desc="Enable RDT">y</RDT_ENABLED>
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<CDP_ENABLED desc="CDP (Code and Data Prioritization). CDP is an extension of CAT.">n</CDP_ENABLED>
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<CLOS_MASK desc="Cache Capacity Bitmask">*0xff*</CLOS_MASK>
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<CLOS_MASK desc="Cache Capacity Bitmask">*0x3f*</CLOS_MASK>
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<CLOS_MASK desc="Cache Capacity Bitmask">*0xf*</CLOS_MASK>
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<CLOS_MASK desc="Cache Capacity Bitmask">*0x3*</CLOS_MASK>
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<MBA_DELAY desc="Memory Bandwidth Allocation delay value">*0*</MBA_DELAY>
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</RDT>
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.. note::
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Users can change the mask values, but the cache mask must have
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**continuous bits** or a #GP fault can be triggered. Similarly, when
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programming an MBA delay value, be sure to set the value to less than or
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equal to the MAX delay value.
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#. Configure each CPU in VMs to a desired CLOS ID in the ``VM`` section of the
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scenario file. Follow `RDT detection and resource capabilities`_
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to identify the maximum supported CLOS ID that can be used. ACRN uses
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**the lowest common MAX CLOS** value among all RDT resources to avoid
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resource misconfigurations.
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.. code-block:: none
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:emphasize-lines: 5,6,7,8
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<vm id="0">
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<vm_type desc="Specify the VM type" readonly="true">PRE_STD_VM</vm_type>
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<name desc="Specify the VM name which will be shown in hypervisor console command: vm_list.">ACRN PRE-LAUNCHED VM0</name>
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<uuid configurable="0" desc="vm uuid">26c5e0d8-8f8a-47d8-8109-f201ebd61a5e</uuid>
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<clos desc="Class of Service for Cache Allocation Technology. Please refer SDM 17.19.2 for details and use with caution.">
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<vcpu_clos>*0*</vcpu_clos>
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<vcpu_clos>*1*</vcpu_clos>
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</clos>
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</vm>
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.. note::
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In ACRN, Lower CLOS always means higher priority (CLOS 0 > CLOS 1 > CLOS 2 > ... CLOS n).
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So, carefully program each VM's CLOS accordingly.
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#. Careful consideration should be made when assigning vCPU affinity. In
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a cache isolation configuration, in addition to isolating CAT-capable
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caches, you must also isolate lower-level caches. In the following
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example, logical processor #0 and #2 share L1 and L2 caches. In this
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case, do not assign LP #0 and LP #2 to different VMs that need to do
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cache isolation. Assign LP #1 and LP #3 with similar consideration:
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.. code-block:: none
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:emphasize-lines: 3
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# lstopo-no-graphics -v
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Package L#0 (P#0 CPUVendor=GenuineIntel CPUFamilyNumber=6 CPUModelNumber=142)
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L3Cache L#0 (size=3072KB linesize=64 ways=12 Inclusive=1)
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L2Cache L#0 (size=256KB linesize=64 ways=4 Inclusive=0)
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L1dCache L#0 (size=32KB linesize=64 ways=8 Inclusive=0)
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L1iCache L#0 (size=32KB linesize=64 ways=8 Inclusive=0)
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Core L#0 (P#0)
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PU L#0 (P#0)
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PU L#1 (P#2)
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L2Cache L#1 (size=256KB linesize=64 ways=4 Inclusive=0)
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L1dCache L#1 (size=32KB linesize=64 ways=8 Inclusive=0)
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L1iCache L#1 (size=32KB linesize=64 ways=8 Inclusive=0)
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Core L#1 (P#1)
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PU L#2 (P#1)
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PU L#3 (P#3)
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#. Bandwidth control is per-core (not per LP), so max delay values of
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per-LP CLOS is applied to the core. If HT is turned on, don't place high
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priority threads on sibling LPs running lower priority threads.
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#. Based on our scenario, build and install ACRN. See :ref:`build-with-acrn-scenario`
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for building and installing instructions.
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#. Restart the platform.
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