220 lines
6.1 KiB
Python
220 lines
6.1 KiB
Python
# Copyright (C) 2022 Intel Corporation.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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from cpuparser.platformbase import MSR, msrfield
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class MSR_IA32_MISC_ENABLE(MSR):
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addr = 0x1a0
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fast_string = msrfield(1, 0, doc=None)
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capability_bits = [
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"fast_string",
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]
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class MSR_IA32_FEATURE_CONTROL(MSR):
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addr = 0x03a
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msr_ia32_feature_control_lock = msrfield(1, 0, doc=None)
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msr_ia32_feature_control_vmx_no_smx = msrfield(1, 2, doc=None)
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@property
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def disable_vmx(self):
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return self.msr_ia32_feature_control_lock and not self.msr_ia32_feature_control_vmx_no_smx
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capability_bits = [
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"disable_vmx",
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]
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class MSR_IA32_VMX_PROCBASED_CTLS2(MSR):
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addr = 0x0000048B
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@property
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def vmx_procbased_ctls2_vapic(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 0)
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@property
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def vmx_procbased_ctls2_ept(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 1)
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@property
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def vmx_procbased_ctls2_vpid(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 5)
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@property
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def vmx_procbased_ctls2_rdtscp(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 3)
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@property
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def vmx_procbased_ctls2_unrestrict(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 7)
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capability_bits = [
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"vmx_procbased_ctls2_vapic",
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"vmx_procbased_ctls2_ept",
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"vmx_procbased_ctls2_vpid",
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"vmx_procbased_ctls2_rdtscp",
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"vmx_procbased_ctls2_unrestrict",
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]
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class MSR_IA32_VMX_PINBASED_CTLS(MSR):
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addr = 0x00000481
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@property
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def vmx_pinbased_ctls_irq_exit(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 0)
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capability_bits = [
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"vmx_pinbased_ctls_irq_exit",
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]
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class MSR_IA32_VMX_PROCBASED_CTLS(MSR):
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addr = 0x00000482
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@property
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def vmx_procbased_ctls_tsc_off(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 3)
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@property
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def vmx_procbased_ctls_tpr_shadow(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 21)
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@property
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def vmx_procbased_ctls_io_bitmap(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 25)
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@property
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def vmx_procbased_ctls_msr_bitmap(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 28)
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@property
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def vmx_procbased_ctls_hlt(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 7)
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@property
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def vmx_procbased_ctls_secondary(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 31)
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@property
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def ept(self):
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is_ept_supported = False
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if ((self.value >> 32) & (1 << 31)) != 0:
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msr_val = MSR_IA32_VMX_PROCBASED_CTLS2.rdmsr(self.cpu_id)
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if msrfield.is_ctrl_setting_allowed(msr_val.value, 1 << 1):
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is_ept_supported = True
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return is_ept_supported
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@property
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def apicv(self):
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features = 0
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vapic_feature_tpr_shadow = 1 << 3
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vapic_feature_virt_access = 1 << 0
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vapic_feature_vx2apic_mode = 1 << 5
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vapic_feature_virt_reg = 1 << 1
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vapic_feature_intr_delivery = 1 << 2
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vapic_feature_post_intr = 1 << 4
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if msrfield.is_ctrl_setting_allowed(self.value, 1 << 21):
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features |= vapic_feature_tpr_shadow
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msr_val = MSR_IA32_VMX_PROCBASED_CTLS2.rdmsr(self.cpu_id)
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if msrfield.is_ctrl_setting_allowed(msr_val.value, 1 << 0):
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features |= vapic_feature_virt_access
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if msrfield.is_ctrl_setting_allowed(msr_val.value, 1 << 4):
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features |= vapic_feature_vx2apic_mode
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if msrfield.is_ctrl_setting_allowed(msr_val.value, 1 << 8):
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features |= vapic_feature_virt_reg
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if msrfield.is_ctrl_setting_allowed(msr_val.value, 1 << 9):
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features |= vapic_feature_intr_delivery
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msr_val = MSR_IA32_VMX_PINBASED_CTLS.rdmsr(self.cpu_id)
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if msrfield.is_ctrl_setting_allowed(msr_val.value, 1 << 7):
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features |= vapic_feature_post_intr
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apicv_basic_feature = (vapic_feature_tpr_shadow | vapic_feature_virt_access | vapic_feature_vx2apic_mode)
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return (features & apicv_basic_feature) == apicv_basic_feature
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capability_bits = [
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"ept",
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"apicv",
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"vmx_procbased_ctls_tsc_off",
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"vmx_procbased_ctls_tpr_shadow",
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"vmx_procbased_ctls_io_bitmap",
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"vmx_procbased_ctls_msr_bitmap",
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"vmx_procbased_ctls_hlt",
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"vmx_procbased_ctls_secondary",
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]
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class MSR_IA32_VMX_EPT_VPID_CAP(MSR):
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addr = 0x0000048C
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invept = msrfield(1, 20)
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ept_2mb_page = msrfield(1, 16)
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vmx_ept_1gb_page = msrfield(1, 17)
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invvpid = msrfield(1, 32) and msrfield(1, 41) and msrfield(1, 42)
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capability_bits = [
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"invept",
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"invvpid",
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"ept_2mb_page",
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"vmx_ept_1gb_page",
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]
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class MSR_IA32_VMX_MISC(MSR):
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addr = 0x00000485
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unrestricted_guest = msrfield(1, 5)
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capability_bits = [
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"unrestricted_guest",
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]
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class MSR_IA32_VMX_BASIC(MSR):
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addr = 0x00000480
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set_32bit_addr_width = msrfield(1, 48)
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capability_bits = [
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"set_32bit_addr_width",
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]
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class MSR_IA32_VMX_EXIT_CTLS(MSR):
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addr = 0x00000483
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@property
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def vmx_exit_ctls_ack_irq(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 15)
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@property
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def vmx_exit_ctls_save_pat(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 18)
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@property
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def vmx_exit_ctls_load_pat(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 19)
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@property
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def vmx_exit_ctls_host_addr64(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 9)
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capability_bits = [
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"vmx_exit_ctls_ack_irq",
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"vmx_exit_ctls_save_pat",
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"vmx_exit_ctls_load_pat",
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"vmx_exit_ctls_host_addr64",
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]
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class MSR_IA32_VMX_ENTRY_CTLS(MSR):
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addr = 0x00000484
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@property
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def vmx_entry_ctls_load_pat(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 14)
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@property
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def vmx_entry_ctls_ia32e_mode(self):
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return msrfield.is_vmx_cap_supported(self, 1 << 9)
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capability_bits = [
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"vmx_entry_ctls_load_pat",
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"vmx_entry_ctls_ia32e_mode",
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]
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