290 lines
6.9 KiB
C
290 lines
6.9 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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#include <softirq.h>
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#define MAX_TIMER_ACTIONS 32U
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#define CAL_MS 10U
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#define MIN_TIMER_PERIOD_US 500U
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uint32_t tsc_khz = 0U;
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static void run_timer(const struct hv_timer *timer)
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{
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/* deadline = 0 means stop timer, we should skip */
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if ((timer->func != NULL) && (timer->fire_tsc != 0UL)) {
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timer->func(timer->priv_data);
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}
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TRACE_2L(TRACE_TIMER_ACTION_PCKUP, timer->fire_tsc, 0UL);
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}
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/* run in interrupt context */
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static void tsc_deadline_handler(__unused uint32_t irq, __unused void *data)
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{
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fire_softirq(SOFTIRQ_TIMER);
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}
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static inline void update_physical_timer(struct per_cpu_timers *cpu_timer)
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{
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struct hv_timer *timer = NULL;
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/* find the next event timer */
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if (!list_empty(&cpu_timer->timer_list)) {
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timer = list_entry((&cpu_timer->timer_list)->next,
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struct hv_timer, node);
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/* it is okay to program a expired time */
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msr_write(MSR_IA32_TSC_DEADLINE, timer->fire_tsc);
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}
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}
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static void local_add_timer(struct per_cpu_timers *cpu_timer,
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struct hv_timer *timer,
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bool *need_update)
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{
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struct list_head *pos, *prev;
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struct hv_timer *tmp;
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uint64_t tsc = timer->fire_tsc;
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prev = &cpu_timer->timer_list;
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list_for_each(pos, &cpu_timer->timer_list) {
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tmp = list_entry(pos, struct hv_timer, node);
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if (tmp->fire_tsc < tsc) {
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prev = &tmp->node;
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}
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else {
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break;
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}
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}
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list_add(&timer->node, prev);
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if (need_update != NULL) {
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/* update the physical timer if we're on the timer_list head */
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*need_update = (prev == &cpu_timer->timer_list);
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}
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}
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int add_timer(struct hv_timer *timer)
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{
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struct per_cpu_timers *cpu_timer;
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uint16_t pcpu_id;
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bool need_update;
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if ((timer == NULL) || (timer->func == NULL) || (timer->fire_tsc == 0UL)) {
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return -EINVAL;
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}
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ASSERT(list_empty(&timer->node), "add timer again!\n");
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/* limit minimal periodic timer cycle period */
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if (timer->mode == TICK_MODE_PERIODIC) {
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timer->period_in_cycle = max(timer->period_in_cycle,
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us_to_ticks(MIN_TIMER_PERIOD_US));
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}
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pcpu_id = get_cpu_id();
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cpu_timer = &per_cpu(cpu_timers, pcpu_id);
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local_add_timer(cpu_timer, timer, &need_update);
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if (need_update) {
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update_physical_timer(cpu_timer);
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}
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TRACE_2L(TRACE_TIMER_ACTION_ADDED, timer->fire_tsc, 0UL);
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return 0;
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}
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void del_timer(struct hv_timer *timer)
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{
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if ((timer != NULL) && !list_empty(&timer->node)) {
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list_del_init(&timer->node);
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}
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}
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static void init_percpu_timer(uint16_t pcpu_id)
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{
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struct per_cpu_timers *cpu_timer;
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cpu_timer = &per_cpu(cpu_timers, pcpu_id);
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INIT_LIST_HEAD(&cpu_timer->timer_list);
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}
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static void init_tsc_deadline_timer(void)
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{
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uint32_t val;
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val = VECTOR_TIMER;
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val |= APIC_LVTT_TM_TSCDLT; /* TSC deadline and unmask */
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msr_write(MSR_IA32_EXT_APIC_LVT_TIMER, val);
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cpu_memory_barrier();
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/* disarm timer */
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msr_write(MSR_IA32_TSC_DEADLINE, 0UL);
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}
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static void timer_softirq(uint16_t pcpu_id)
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{
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struct per_cpu_timers *cpu_timer;
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struct hv_timer *timer;
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struct list_head *pos, *n;
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int tries = MAX_TIMER_ACTIONS;
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uint64_t current_tsc = rdtsc();
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/* handle passed timer */
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cpu_timer = &per_cpu(cpu_timers, pcpu_id);
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/* This is to make sure we are not blocked due to delay inside func()
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* force to exit irq handler after we serviced >31 timers
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* caller used to local_add_timer() for periodic timer, if there is a delay
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* inside func(), it will infinitely loop here, because new added timer
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* already passed due to previously func()'s delay.
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*/
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list_for_each_safe(pos, n, &cpu_timer->timer_list) {
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timer = list_entry(pos, struct hv_timer, node);
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/* timer expried */
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tries--;
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if ((timer->fire_tsc <= current_tsc) && (tries > 0)) {
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del_timer(timer);
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run_timer(timer);
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if (timer->mode == TICK_MODE_PERIODIC) {
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/* update periodic timer fire tsc */
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timer->fire_tsc += timer->period_in_cycle;
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local_add_timer(cpu_timer, timer, NULL);
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}
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} else {
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break;
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}
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}
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/* update nearest timer */
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update_physical_timer(cpu_timer);
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}
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void timer_init(void)
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{
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uint16_t pcpu_id = get_cpu_id();
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int32_t retval;
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init_percpu_timer(pcpu_id);
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if (pcpu_id == BOOT_CPU_ID) {
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register_softirq(SOFTIRQ_TIMER, timer_softirq);
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retval = request_irq(TIMER_IRQ, (irq_action_t)tsc_deadline_handler,
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NULL, IRQF_NONE);
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if (retval < 0) {
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pr_err("Timer setup failed");
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return;
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}
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}
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init_tsc_deadline_timer();
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}
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void check_tsc(void)
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{
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uint64_t temp64;
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/* Ensure time-stamp timer is turned on for each CPU */
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CPU_CR_READ(cr4, &temp64);
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CPU_CR_WRITE(cr4, (temp64 & ~CR4_TSD));
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}
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static uint64_t pit_calibrate_tsc(uint32_t cal_ms_arg)
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{
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#define PIT_TICK_RATE 1193182U
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#define PIT_TARGET 0x3FFFU
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#define PIT_MAX_COUNT 0xFFFFU
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uint32_t cal_ms = cal_ms_arg;
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uint32_t initial_pit;
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uint16_t current_pit;
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uint32_t max_cal_ms;
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uint64_t current_tsc;
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uint8_t initial_pit_high, initial_pit_low;
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max_cal_ms = ((PIT_MAX_COUNT - PIT_TARGET) * 1000U) / PIT_TICK_RATE;
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cal_ms = min(cal_ms, max_cal_ms);
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/* Assume the 8254 delivers 18.2 ticks per second when 16 bits fully
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* wrap. This is about 1.193MHz or a clock period of 0.8384uSec
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*/
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initial_pit = (cal_ms * PIT_TICK_RATE) / 1000U;
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initial_pit += PIT_TARGET;
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initial_pit_high = (uint8_t)(initial_pit >> 8U);
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initial_pit_low = (uint8_t)initial_pit;
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/* Port 0x43 ==> Control word write; Data 0x30 ==> Select Counter 0,
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* Read/Write least significant byte first, mode 0, 16 bits.
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*/
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pio_write8(0x30U, 0x43U);
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pio_write8(initial_pit_low, 0x40U); /* Write LSB */
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pio_write8(initial_pit_high, 0x40U); /* Write MSB */
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current_tsc = rdtsc();
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do {
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/* Port 0x43 ==> Control word write; 0x00 ==> Select
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* Counter 0, Counter Latch Command, Mode 0; 16 bits
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*/
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pio_write8(0x00U, 0x43U);
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current_pit = (uint16_t)pio_read8(0x40U); /* Read LSB */
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current_pit |= (uint16_t)pio_read8(0x40U) << 8U; /* Read MSB */
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/* Let the counter count down to PIT_TARGET */
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} while (current_pit > PIT_TARGET);
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current_tsc = rdtsc() - current_tsc;
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return (current_tsc / cal_ms) * 1000U;
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}
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/*
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* Determine TSC frequency via CPUID 0x15 and 0x16.
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*/
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static uint64_t native_calibrate_tsc(void)
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{
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uint64_t tsc_hz = 0UL;
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if (boot_cpu_data.cpuid_level >= 0x15U) {
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uint32_t eax_denominator, ebx_numerator, ecx_hz, reserved;
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cpuid(0x15U, &eax_denominator, &ebx_numerator,
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&ecx_hz, &reserved);
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if ((eax_denominator != 0U) && (ebx_numerator != 0U)) {
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tsc_hz = ((uint64_t) ecx_hz *
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ebx_numerator) / eax_denominator;
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}
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}
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if ((tsc_hz == 0UL) && (boot_cpu_data.cpuid_level >= 0x16U)) {
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uint32_t eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
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cpuid(0x16U, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
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tsc_hz = (uint64_t) eax_base_mhz * 1000000U;
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}
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return tsc_hz;
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}
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void calibrate_tsc(void)
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{
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uint64_t tsc_hz;
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tsc_hz = native_calibrate_tsc();
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if (tsc_hz == 0U) {
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tsc_hz = pit_calibrate_tsc(CAL_MS);
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}
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tsc_khz = (uint32_t)(tsc_hz / 1000UL);
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printf("%s, tsc_khz=%lu\n", __func__, tsc_khz);
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}
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