148 lines
4.6 KiB
C
148 lines
4.6 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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/* The table includes cpu px info of Intel A3960 SoC */
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static const struct cpu_px_data px_a3960[] = {
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{0x960, 0, 0xA, 0xA, 0x1800, 0x1800}, /* P0 */
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{0x8FC, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P1 */
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{0x898, 0, 0xA, 0xA, 0x1600, 0x1600}, /* P2 */
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{0x834, 0, 0xA, 0xA, 0x1500, 0x1500}, /* P3 */
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{0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P4 */
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{0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P5 */
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{0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P6 */
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{0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P7 */
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{0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P8 */
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{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P9 */
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{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P10 */
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{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P11 */
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{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P12 */
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{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P13 */
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{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P14 */
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{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P15 */
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{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P16 */
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};
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/* The table includes cpu cx info of Intel A3960 SoC */
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static const struct cpu_cx_data cx_a3960[] = {
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{{SPACE_FFixedHW, 0x0, 0, 0, 0}, 0x1, 0x1, 0x3E8}, /* C1 */
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{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x415}, 0x2, 0x32, 0x0A}, /* C2 */
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{{SPACE_SYSTEM_IO, 0x8, 0, 0, 0x419}, 0x3, 0x96, 0x0A} /* C3 */
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};
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/* The table includes cpu px info of Intel A3950 SoC */
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static const struct cpu_px_data px_a3950[] = {
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{0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P0 */
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{0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P1 */
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{0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P2 */
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{0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P3 */
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{0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P4 */
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{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P5 */
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{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P6 */
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{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P7 */
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{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P8 */
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{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P9 */
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{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P10 */
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{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P11 */
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{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P12 */
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};
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/* The table includes cpu px info of Intel J3455 SoC */
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static const struct cpu_px_data px_j3455[] = {
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{0x5DD, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P0 */
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{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P1 */
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{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P2 */
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{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P3 */
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{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P4 */
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{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P5 */
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{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P6 */
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{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P7 */
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{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P8 */
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};
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/* The table includes cpu cx info of Intel J3455 SoC */
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static const struct cpu_cx_data cx_j3455[] = {
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{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x01}, 0x1, 0x1, 0x3E8}, /* C1 */
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{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x21}, 0x2, 0x32, 0x0A}, /* C2 */
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{{SPACE_FFixedHW, 0x1, 0x2, 0x1, 0x60}, 0x3, 0x96, 0x0A} /* C3 */
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};
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static const struct cpu_state_table {
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char model_name[64];
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struct cpu_state_info state_info;
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} cpu_state_tbl[] = {
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{"Intel(R) Atom(TM) Processor A3960 @ 1.90GHz",
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{ARRAY_SIZE(px_a3960), px_a3960,
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ARRAY_SIZE(cx_a3960), cx_a3960}
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},
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{"Intel(R) Atom(TM) Processor A3950 @ 1.60GHz",
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{ARRAY_SIZE(px_a3950), px_a3950,
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ARRAY_SIZE(cx_a3960), cx_a3960} /* Cx is same as A3960 */
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},
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{"Intel(R) Celeron(R) CPU J3455 @ 1.50GHz",
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{ARRAY_SIZE(px_j3455), px_j3455,
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ARRAY_SIZE(cx_j3455), cx_j3455}
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}
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};
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static int get_state_tbl_idx(char *cpuname)
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{
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int i;
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int count = ARRAY_SIZE(cpu_state_tbl);
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if (cpuname == NULL) {
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return -1;
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}
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for (i = 0; i < count; i++) {
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if (strcmp((cpu_state_tbl[i].model_name),
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cpuname) == 0) {
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return i;
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}
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}
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return -1;
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}
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void load_cpu_state_data(void)
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{
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int tbl_idx;
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const struct cpu_state_info *state_info;
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memset(&boot_cpu_data.state_info, 0,
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sizeof(struct cpu_state_info));
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tbl_idx = get_state_tbl_idx(boot_cpu_data.model_name);
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if (tbl_idx < 0) {
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/* The state table is not found. */
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return;
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}
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state_info = &(cpu_state_tbl + tbl_idx)->state_info;
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if ((state_info->px_cnt != 0U) && (state_info->px_data != NULL)) {
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if (state_info->px_cnt > MAX_PSTATE) {
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boot_cpu_data.state_info.px_cnt = MAX_PSTATE;
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} else {
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boot_cpu_data.state_info.px_cnt = state_info->px_cnt;
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}
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boot_cpu_data.state_info.px_data = state_info->px_data;
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}
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if ((state_info->cx_cnt != 0U) && (state_info->cx_data != NULL)) {
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if (state_info->cx_cnt > MAX_CX_ENTRY) {
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boot_cpu_data.state_info.cx_cnt = MAX_CX_ENTRY;
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} else {
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boot_cpu_data.state_info.cx_cnt = state_info->cx_cnt;
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}
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boot_cpu_data.state_info.cx_data = state_info->cx_data;
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}
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}
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