198 lines
5.3 KiB
ArmAsm
198 lines
5.3 KiB
ArmAsm
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cpu.h>
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#include <mmu.h>
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#include <gdt.h>
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#include <idt.h>
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#include <msr.h>
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/* MULTIBOOT HEADER */
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#define MULTIBOOT_HEADER_MAGIC 0x1badb002
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#define MULTIBOOT_HEADER_FLAGS 0x00000002 /*flags bit 1 : enable mem_*, mmap_**/
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.section multiboot_header, "a"
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.align 4
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/* header magic */
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.long MULTIBOOT_HEADER_MAGIC
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/* header flags - flags bit 6 : enable mmap_* */
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.long MULTIBOOT_HEADER_FLAGS
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/* header checksum = -(magic + flags) */
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.long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
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.section entry, "ax"
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.align 8
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.code32
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.global cpu_primary_start_32
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cpu_primary_start_32:
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/* Disable interrupts */
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cli
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/* Clear direction flag */
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cld
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/* save eax and ebx */
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movl %eax, %esp
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movl %ebx, %ebp
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/* detect whether it is in long mode */
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movl $MSR_IA32_EFER, %ecx
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rdmsr
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test $MSR_IA32_EFER_LMA_BIT, %eax
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/* jump to 64bit entry if it is already in long mode */
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jne cpu_primary_start_64
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/* save the MULTBOOT magic number & MBI */
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movl %esp, (boot_regs)
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movl %ebp, (boot_regs+4)
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/* Disable paging */
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mov %cr0, %ebx
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andl $~CR0_PG, %ebx
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mov %ebx, %cr0
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/* Set DE, PAE, MCE and OS support bits in CR4 */
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movl $(CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT), %eax
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mov %eax, %cr4
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/* Set CR3 to PML4 table address */
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movl $cpu_boot32_page_tables_start, %edi
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mov %edi, %cr3
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/* Set LME bit in EFER */
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movl $MSR_IA32_EFER, %ecx
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rdmsr
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orl $MSR_IA32_EFER_LME_BIT, %eax
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wrmsr
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/* Enable paging, protection, numeric error and co-processor
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monitoring in CR0 to enter long mode */
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mov %cr0, %ebx
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orl $(CR0_PG | CR0_PE | CR0_MP | CR0_NE), %ebx
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mov %ebx, %cr0
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/* Load temportary GDT pointer value */
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mov $cpu_primary32_gdt_ptr, %ebx
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lgdt (%ebx)
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/* Perform a long jump based to start executing in 64-bit mode */
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ljmp $HOST_GDT_RING0_CODE_SEL, $primary_start_long_mode
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.code64
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.org 0x200
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.global cpu_primary_start_64
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cpu_primary_start_64:
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/* save the MULTBOOT magic number & MBI */
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movl %edi, (boot_regs)
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movl %esi, (boot_regs+4)
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primary_start_long_mode:
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/* Fix up the IDT desciptors */
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movl $HOST_IDT, %edx
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movl $HOST_IDT_ENTRIES, %ecx
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.LFixUpIDT_Entries:
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xorl %eax, %eax
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xchgl %eax, 12(%edx) /* Set rsvd bits to 0; eax now has
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high 32 of entry point */
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xchgl %eax, 8(%edx) /* Set bits 63..32 of entry point;
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eax now has low 32 of entry point */
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movw %ax, (%edx) /* Set bits 0-15 of procedure entry
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point */
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shr $16, %eax
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movw %ax, 6(%edx) /* Set bits 16-31 of entry point */
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addl $X64_IDT_DESC_SIZE,%edx
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loop .LFixUpIDT_Entries
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/* Load IDT */
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mov $HOST_IDTR, %rcx
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lidtq (%rcx)
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/* Load temportary GDT pointer value */
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mov $cpu_primary32_gdt_ptr, %ebx
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lgdt (%ebx)
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/* Replace CS with the correct value should we need it */
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mov $HOST_GDT_RING0_CODE_SEL, %bx
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mov %bx, jcs
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movabsq $jmpbuf, %rax
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rex.w ljmp *(%rax)
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.data
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jmpbuf: .quad after
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jcs: .word 0
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.text
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after:
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/* Initialize temporary stack pointer */
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movq $_ld_bss_end, %rsp
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add $CPU_PAGE_SIZE,%rsp
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and $(~(CPU_STACK_ALIGN - 1)),%rsp
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// load all selector registers with appropriate values
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xor %edx, %edx
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lldt %dx
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movl $HOST_GDT_RING0_DATA_SEL,%eax
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mov %eax,%ss // Was 32bit POC Stack
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mov %eax,%ds // Was 32bit POC Data
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mov %eax,%es // Was 32bit POC Data
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mov %edx,%fs // Was 32bit POC Data
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mov %edx,%gs // Was 32bit POC CLS
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/* Push sp magic to top of stack for call trace */
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pushq $SP_BOTTOM_MAGIC
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/* continue with chipset level initialization */
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call bsp_boot_init
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loop:
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jmp loop
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.align 4
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.global boot_regs
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boot_regs:
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.long 0x00000000
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.long 0x00000000
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/* GDT table */
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.align 4
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cpu_primary32_gdt:
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.quad 0x0000000000000000
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.quad 0x00af9b000000ffff
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.quad 0x00cf93000000ffff
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cpu_primary32_gdt_end:
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/* GDT pointer */
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.align 2
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cpu_primary32_gdt_ptr:
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.short (cpu_primary32_gdt_end - cpu_primary32_gdt) - 1
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.quad cpu_primary32_gdt
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/* PML4, PDPT, and PD tables initialized to map first 4 GBytes of memory */
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.align CPU_PAGE_SIZE
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.global cpu_boot32_page_tables_start
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cpu_boot32_page_tables_start:
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.quad cpu_primary32_pdpt_addr + (IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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.align CPU_PAGE_SIZE
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cpu_primary32_pdpt_addr:
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address = 0
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.rept 4
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.quad cpu_primary32_pdt_addr + address + \
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(IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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address = address + CPU_PAGE_SIZE
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.endr
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.align CPU_PAGE_SIZE
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cpu_primary32_pdt_addr:
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address = 0
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.rept 2048
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.quad address + (IA32E_PDPTE_PS_BIT | IA32E_COMM_P_BIT | IA32E_COMM_RW_BIT)
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address = address + 0x200000
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.endr
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