86 lines
3.8 KiB
C
86 lines
3.8 KiB
C
/*-
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef VLAPIC_PRIV_H
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#define VLAPIC_PRIV_H
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/*
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* APIC Register: Offset Description
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*/
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#define APIC_OFFSET_ID 0x20U /* Local APIC ID */
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#define APIC_OFFSET_VER 0x30U /* Local APIC Version */
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#define APIC_OFFSET_TPR 0x80U /* Task Priority Register */
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#define APIC_OFFSET_APR 0x90U /* Arbitration Priority */
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#define APIC_OFFSET_PPR 0xA0U /* Processor Priority Register */
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#define APIC_OFFSET_EOI 0xB0U /* EOI Register */
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#define APIC_OFFSET_RRR 0xC0U /* Remote read */
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#define APIC_OFFSET_LDR 0xD0U /* Logical Destination */
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#define APIC_OFFSET_DFR 0xE0U /* Destination Format Register */
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#define APIC_OFFSET_SVR 0xF0U /* Spurious Vector Register */
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#define APIC_OFFSET_ISR0 0x100U /* In Service Register */
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#define APIC_OFFSET_ISR1 0x110U
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#define APIC_OFFSET_ISR2 0x120U
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#define APIC_OFFSET_ISR3 0x130U
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#define APIC_OFFSET_ISR4 0x140U
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#define APIC_OFFSET_ISR5 0x150U
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#define APIC_OFFSET_ISR6 0x160U
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#define APIC_OFFSET_ISR7 0x170U
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#define APIC_OFFSET_TMR0 0x180U /* Trigger Mode Register */
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#define APIC_OFFSET_TMR1 0x190U
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#define APIC_OFFSET_TMR2 0x1A0U
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#define APIC_OFFSET_TMR3 0x1B0U
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#define APIC_OFFSET_TMR4 0x1C0U
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#define APIC_OFFSET_TMR5 0x1D0U
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#define APIC_OFFSET_TMR6 0x1E0U
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#define APIC_OFFSET_TMR7 0x1F0U
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#define APIC_OFFSET_IRR0 0x200U /* Interrupt Request Register */
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#define APIC_OFFSET_IRR1 0x210U
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#define APIC_OFFSET_IRR2 0x220U
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#define APIC_OFFSET_IRR3 0x230U
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#define APIC_OFFSET_IRR4 0x240U
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#define APIC_OFFSET_IRR5 0x250U
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#define APIC_OFFSET_IRR6 0x260U
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#define APIC_OFFSET_IRR7 0x270U
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#define APIC_OFFSET_ESR 0x280U /* Error Status Register */
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#define APIC_OFFSET_CMCI_LVT 0x2F0U /* Local Vector Table (CMCI) */
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#define APIC_OFFSET_ICR_LOW 0x300U /* Interrupt Command Register */
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#define APIC_OFFSET_ICR_HI 0x310U
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#define APIC_OFFSET_TIMER_LVT 0x320U /* Local Vector Table (Timer) */
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#define APIC_OFFSET_THERM_LVT 0x330U /* Local Vector Table (Thermal) */
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#define APIC_OFFSET_PERF_LVT 0x340U /* Local Vector Table (PMC) */
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#define APIC_OFFSET_LINT0_LVT 0x350U /* Local Vector Table (LINT0) */
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#define APIC_OFFSET_LINT1_LVT 0x360U /* Local Vector Table (LINT1) */
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#define APIC_OFFSET_ERROR_LVT 0x370U /* Local Vector Table (ERROR) */
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#define APIC_OFFSET_TIMER_ICR 0x380U /* Timer's Initial Count */
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#define APIC_OFFSET_TIMER_CCR 0x390U /* Timer's Current Count */
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#define APIC_OFFSET_TIMER_DCR 0x3E0U /* Timer's Divide Configuration */
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#define APIC_OFFSET_SELF_IPI 0x3F0U /* Self IPI Register */
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#endif /* VLAPIC_PRIV_H */
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