138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* BIOS Information
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* Vendor: Intel Corporation
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* Version: EHLSFWI1.R00.2224.A00.2005281500
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* Release Date: 05/28/2020
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*
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* Base Board Information
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* Manufacturer: Intel Corporation
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* Product Name: ElkhartLake LPDDR4x T3 CRB
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* Version: 2
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*/
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#include <board.h>
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#include <vtd.h>
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#include <msr.h>
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#include <pci.h>
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#include <misc_cfg.h>
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static struct dmar_dev_scope drhd0_dev_scope[DRHD0_DEV_CNT] = {
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{
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.type = DRHD0_DEVSCOPE0_TYPE,
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.id = DRHD0_DEVSCOPE0_ID,
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.bus = DRHD0_DEVSCOPE0_BUS,
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.devfun = DRHD0_DEVSCOPE0_PATH,
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},
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};
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static struct dmar_dev_scope drhd1_dev_scope[DRHD1_DEV_CNT] = {
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{
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.type = DRHD1_DEVSCOPE0_TYPE,
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.id = DRHD1_DEVSCOPE0_ID,
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.bus = DRHD1_DEVSCOPE0_BUS,
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.devfun = DRHD1_DEVSCOPE0_PATH,
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},
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{
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.type = DRHD1_DEVSCOPE1_TYPE,
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.id = DRHD1_DEVSCOPE1_ID,
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.bus = DRHD1_DEVSCOPE1_BUS,
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.devfun = DRHD1_DEVSCOPE1_PATH,
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},
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};
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static struct dmar_dev_scope drhd2_dev_scope[DRHD2_DEV_CNT] = {
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{
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.type = DRHD2_DEVSCOPE0_TYPE,
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.id = DRHD2_DEVSCOPE0_ID,
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.bus = DRHD2_DEVSCOPE0_BUS,
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.devfun = DRHD2_DEVSCOPE0_PATH,
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},
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{
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.type = DRHD2_DEVSCOPE1_TYPE,
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.id = DRHD2_DEVSCOPE1_ID,
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.bus = DRHD2_DEVSCOPE1_BUS,
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.devfun = DRHD2_DEVSCOPE1_PATH,
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},
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{
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.type = DRHD2_DEVSCOPE2_TYPE,
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.id = DRHD2_DEVSCOPE2_ID,
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.bus = DRHD2_DEVSCOPE2_BUS,
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.devfun = DRHD2_DEVSCOPE2_PATH,
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},
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};
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static struct dmar_drhd drhd_info_array[DRHD_COUNT] = {
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{
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.dev_cnt = DRHD0_DEV_CNT,
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.segment = DRHD0_SEGMENT,
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.flags = DRHD0_FLAGS,
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.reg_base_addr = DRHD0_REG_BASE,
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.ignore = DRHD0_IGNORE,
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.devices = drhd0_dev_scope
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},
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{
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.dev_cnt = DRHD1_DEV_CNT,
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.segment = DRHD1_SEGMENT,
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.flags = DRHD1_FLAGS,
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.reg_base_addr = DRHD1_REG_BASE,
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.ignore = DRHD1_IGNORE,
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.devices = drhd1_dev_scope
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},
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{
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.dev_cnt = DRHD2_DEV_CNT,
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.segment = DRHD2_SEGMENT,
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.flags = DRHD2_FLAGS,
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.reg_base_addr = DRHD2_REG_BASE,
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.ignore = DRHD2_IGNORE,
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.devices = drhd2_dev_scope
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},
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};
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struct dmar_info plat_dmar_info = {
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.drhd_count = DRHD_COUNT,
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.drhd_units = drhd_info_array,
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};
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#ifdef CONFIG_RDT_ENABLED
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struct platform_clos_info platform_l2_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
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struct platform_clos_info platform_l3_clos_array[MAX_CACHE_CLOS_NUM_ENTRIES];
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struct platform_clos_info platform_mba_clos_array[MAX_MBA_CLOS_NUM_ENTRIES];
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#endif
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static const struct cpu_cx_data board_cpu_cx[3] = {
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{{SPACE_FFixedHW, 0x00U, 0x00U, 0x00U, 0x00UL}, 0x01U, 0x01U, 0x00U}, /* C1 */
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{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1816UL}, 0x02U, 0xFDU, 0x00U}, /* C2 */
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{{SPACE_SYSTEM_IO, 0x08U, 0x00U, 0x00U, 0x1819UL}, 0x03U, 0x418U, 0x00U}, /* C3 */
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};
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static const struct cpu_px_data board_cpu_px[2] = {
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{0x5DDUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P0 */
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{0x5DCUL, 0x00UL, 0x0AUL, 0x0AUL, 0x000F00UL, 0x000F00UL}, /* P1 */
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};
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const struct cpu_state_table board_cpu_state_tbl = {
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"Genuine Intel(R) CPU 0000 @ 1.50GHz",
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{(uint8_t)ARRAY_SIZE(board_cpu_px), board_cpu_px,
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(uint8_t)ARRAY_SIZE(board_cpu_cx), board_cpu_cx}
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};
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const union pci_bdf plat_hidden_pdevs[MAX_HIDDEN_PDEVS_NUM];
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#define VMSIX_ON_MSI_DEV0 .bdf.bits = {.b = 0x00U, .d = 0x1eU, .f =0x4U},
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#define VMSIX_ON_MSI_DEV1 .bdf.bits = {.b = 0x00U, .d = 0x1dU, .f =0x1U},
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#define VMSIX_ON_MSI_DEV2 .bdf.bits = {.b = 0x00U, .d = 0x1dU, .f =0x2U},
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#define VMSIX_ON_MSI_DEV3 .bdf.bits = {.b = 0x00U, .d = 0x13U, .f =0x4U},
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#define VMSIX_ON_MSI_DEV4 .bdf.bits = {.b = 0x00U, .d = 0x13U, .f =0x5U},
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const struct vmsix_on_msi_info vmsix_on_msi_devs[MAX_VMSIX_ON_MSI_PDEVS_NUM] = {
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{VMSIX_ON_MSI_DEV0},
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{VMSIX_ON_MSI_DEV1},
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{VMSIX_ON_MSI_DEV2},
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{VMSIX_ON_MSI_DEV3},
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{VMSIX_ON_MSI_DEV4},
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};
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