87 lines
3.8 KiB
C
87 lines
3.8 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __X86_CPUFEATURES_H__
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#define __X86_CPUFEATURES_H__
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/* Intel-defined CPU features, CPUID level 0x00000001 (ECX)*/
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#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5) + 0)
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#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5) + 1)
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#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5) + 2)
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#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5) + 3)
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#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5) + 4)
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#define X86_FEATURE_VMX ((FEAT_1_ECX << 5) + 5)
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#define X86_FEATURE_SMX ((FEAT_1_ECX << 5) + 6)
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#define X86_FEATURE_EST ((FEAT_1_ECX << 5) + 7)
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#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5) + 8)
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#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5) + 9)
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#define X86_FEATURE_CID ((FEAT_1_ECX << 5) + 10)
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#define X86_FEATURE_FMA ((FEAT_1_ECX << 5) + 12)
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#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5) + 13)
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#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5) + 14)
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#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5) + 15)
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#define X86_FEATURE_PCID ((FEAT_1_ECX << 5) + 17)
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#define X86_FEATURE_DCA ((FEAT_1_ECX << 5) + 18)
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#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5) + 19)
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#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5) + 20)
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#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5) + 21)
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#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5) + 22)
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#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5) + 23)
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#define X86_FEATURE_TSC_DEADLINE ((FEAT_1_ECX << 5) + 24)
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#define X86_FEATURE_AES ((FEAT_1_ECX << 5) + 25)
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#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5) + 26)
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#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5) + 27)
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#define X86_FEATURE_AVX ((FEAT_1_ECX << 5) + 28)
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/* Intel-defined CPU features, CPUID level 0x00000001 (EDX)*/
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#define X86_FEATURE_FPU ((FEAT_1_EDX << 5) + 0)
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#define X86_FEATURE_VME ((FEAT_1_EDX << 5) + 1)
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#define X86_FEATURE_DE ((FEAT_1_EDX << 5) + 2)
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#define X86_FEATURE_PSE ((FEAT_1_EDX << 5) + 3)
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#define X86_FEATURE_TSC ((FEAT_1_EDX << 5) + 4)
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#define X86_FEATURE_MSR ((FEAT_1_EDX << 5) + 5)
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#define X86_FEATURE_PAE ((FEAT_1_EDX << 5) + 6)
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#define X86_FEATURE_MCE ((FEAT_1_EDX << 5) + 7)
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#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5) + 8)
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#define X86_FEATURE_APIC ((FEAT_1_EDX << 5) + 9)
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#define X86_FEATURE_SEP ((FEAT_1_EDX << 5) + 11)
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#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5) + 12)
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#define X86_FEATURE_PGE ((FEAT_1_EDX << 5) + 13)
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#define X86_FEATURE_MCA ((FEAT_1_EDX << 5) + 14)
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#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5) + 15)
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#define X86_FEATURE_PAT ((FEAT_1_EDX << 5) + 16)
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#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5) + 17)
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#define X86_FEATURE_PSN ((FEAT_1_EDX << 5) + 18)
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#define X86_FEATURE_CLF ((FEAT_1_EDX << 5) + 19)
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#define X86_FEATURE_DTES ((FEAT_1_EDX << 5) + 21)
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#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5) + 22)
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#define X86_FEATURE_MMX ((FEAT_1_EDX << 5) + 23)
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#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5) + 24)
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#define X86_FEATURE_SSE ((FEAT_1_EDX << 5) + 25)
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#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5) + 26)
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#define X86_FEATURE_SS ((FEAT_1_EDX << 5) + 27)
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#define X86_FEATURE_HTT ((FEAT_1_EDX << 5) + 28)
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#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5) + 29)
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#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5) + 30)
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#define X86_FEATURE_PBE ((FEAT_1_EDX << 5) + 31)
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/* Intel-defined CPU features, CPUID level 0x00000007 (EBX)*/
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#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5) + 1)
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#define X86_FEATURE_SMEP ((FEAT_7_0_EBX << 5) + 7)
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#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5) + 10)
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#define X86_FEATURE_SMAP ((FEAT_7_0_EBX << 5) + 20)
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/* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/
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#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5) + 26)
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#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5) + 27)
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/* Intel-defined CPU features, CPUID level 0x80000001 (EDX)*/
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#define X86_FEATURE_NX ((FEAT_8000_0001_EDX << 5) + 20)
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#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5) + 26)
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#define X86_FEATURE_LM ((FEAT_8000_0001_EDX << 5) + 29)
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#endif /*__X86_CPUFEATURES_H__*/
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