70 lines
1.4 KiB
C
70 lines
1.4 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation.
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _NPK_H_
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#define _NPK_H_
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#define NPK_DRV_SYSFS_PATH "/sys/bus/pci/drivers/intel_th_pci"
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#define NPK_CSR_MTB_BAR_SZ 0x100000
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#define NPK_CSR_GTH_BASE 0
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#define NPK_CSR_GTH_SZ 0xF0
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#define NPK_CSR_GTHOPT0 0x0
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#define NPK_CSR_SWDEST_0 0x8
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#define NPK_CSR_GSWDEST 0x88
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#define NPK_CSR_GTHSTAT 0xD4
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#define NPK_CSR_GTHSTAT_PLE 0xFF
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#define NPK_CSR_STH_BASE 0x4000
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#define NPK_CSR_STH_SZ 0x80
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#define NPK_CSR_STHCAP0 0x0
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#define NPK_CSR_STHCAP1 0x4
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#define NPK_CSR_MSC0_BASE 0xA0100
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#define NPK_CSR_MSC0_SZ 0x20
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#define NPK_CSR_MSCxCTL 0x0
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#define NPK_CSR_MSCxSTS 0x4
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#define NPK_CSR_MSCxSTS_PLE 0x4
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#define NPK_CSR_MSC1_BASE 0xA0200
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#define NPK_CSR_MSC1_SZ 0x20
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#define NPK_CSR_PTI_BASE 0x1C00
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#define NPK_CSR_PTI_SZ 0x4
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#define NPK_SW_MSTR_STRT 256
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#define NPK_SW_MSTR_STP 1024
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#define NPK_SW_MSTR_NUM (NPK_SW_MSTR_STP - NPK_SW_MSTR_STRT)
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#define NPK_CHANNELS_PER_MSTR 128
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#define NPK_MSTR_TO_MEM_SZ(x) ((x) * NPK_CHANNELS_PER_MSTR * 64)
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enum npk_regs_name {
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NPK_CSR_FIRST,
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NPK_CSR_GTH = NPK_CSR_FIRST,
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NPK_CSR_STH,
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NPK_CSR_MSC0,
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NPK_CSR_MSC1,
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NPK_CSR_PTI,
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NPK_CSR_LAST,
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};
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struct npk_regs {
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uint32_t base;
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uint32_t size;
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union {
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uint8_t *u8;
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uint32_t *u32;
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} data;
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} __packed;
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struct npk_reg_default_val {
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enum npk_regs_name csr;
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int offset;
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uint32_t default_val;
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};
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#endif /* _NPK_H_ */
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