298 lines
7.5 KiB
C
298 lines
7.5 KiB
C
/*
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* Microsoft Hyper-V emulation. See Microsoft's
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* Hypervisor Top Level Functional Specification for more information.
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*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <asm/guest/vm.h>
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#include <logmsg.h>
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#include <asm/vmx.h>
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#include <asm/guest/hyperv.h>
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#include <asm/tsc.h>
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#define DBG_LEVEL_HYPERV 6U
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/* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) */
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#define CPUID3A_TIME_REF_COUNT_MSR (1U << 1U)
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/* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) */
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#define CPUID3A_HYPERCALL_MSR (1U << 5U)
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/* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) */
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#define CPUID3A_VP_INDEX_MSR (1U << 6U)
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/* Partition reference TSC MSR (HV_X64_MSR_REFERENCE_TSC) */
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#define CPUID3A_REFERENCE_TSC_MSR (1U << 9U)
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struct HV_REFERENCE_TSC_PAGE {
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uint32_t tsc_sequence;
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uint32_t reserved1;
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uint64_t tsc_scale;
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uint64_t tsc_offset;
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uint64_t reserved2[509];
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};
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static inline uint64_t
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u64_shl64_div_u64(uint64_t a, uint64_t divisor)
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{
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uint64_t ret, tmp;
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asm volatile ("divq %2" :
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"=a" (ret), "=d" (tmp) :
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"rm" (divisor), "0" (0U), "1" (a));
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return ret;
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}
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static inline uint64_t
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u64_mul_u64_shr64(uint64_t a, uint64_t b)
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{
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uint64_t ret, disc;
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asm volatile ("mulq %3" :
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"=d" (ret), "=a" (disc) :
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"a" (a), "r" (b));
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return ret;
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}
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static void
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hyperv_setup_tsc_page(const struct acrn_vcpu *vcpu, uint64_t val)
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{
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union hyperv_ref_tsc_page_msr *ref_tsc_page = &vcpu->vm->arch_vm.hyperv.ref_tsc_page;
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struct HV_REFERENCE_TSC_PAGE *p;
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uint32_t tsc_seq;
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ref_tsc_page->val64 = val;
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if (ref_tsc_page->enabled == 1U) {
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p = (struct HV_REFERENCE_TSC_PAGE *)gpa2hva(vcpu->vm, ref_tsc_page->gpfn << PAGE_SHIFT);
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if (p != NULL) {
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stac();
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p->tsc_scale = vcpu->vm->arch_vm.hyperv.tsc_scale;
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p->tsc_offset = vcpu->vm->arch_vm.hyperv.tsc_offset;
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cpu_write_memory_barrier();
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tsc_seq = p->tsc_sequence + 1U;
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if ((tsc_seq == 0xFFFFFFFFU) || (tsc_seq == 0U)) {
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tsc_seq = 1U;
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}
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p->tsc_sequence = tsc_seq;
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clac();
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}
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}
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}
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static inline uint64_t
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hyperv_scale_tsc(uint64_t scale)
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{
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uint64_t tsc;
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tsc = rdtsc() + exec_vmread64(VMX_TSC_OFFSET_FULL);
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return u64_mul_u64_shr64(tsc, scale);
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}
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static inline uint64_t
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hyperv_get_ReferenceTime(struct acrn_vm *vm)
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{
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return hyperv_scale_tsc(vm->arch_vm.hyperv.tsc_scale) - vm->arch_vm.hyperv.tsc_offset;
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}
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static void
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hyperv_setup_hypercall_page(const struct acrn_vcpu *vcpu, uint64_t val)
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{
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union hyperv_hypercall_msr hypercall;
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uint64_t page_gpa;
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void *page_hva;
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/*
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* All enlightened versions of Windows operating systems invoke guest hypercalls on
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* the basis of the recommendations presented by the hypervisor in CPUID.40000004:EAX.
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* A conforming hypervisor must return HV_STATUS_INVALID_HYPERCALL_CODE for any
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* unimplemented hypercalls.
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* ACRN does not wish to handle any hypercalls at moment, the following hypercall
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* code page is implemented for this purpose.
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* inst32[] for 32 bits:
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* mov eax, 0x02 ; HV_STATUS_INVALID_HYPERCALL_CODE
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* mov edx, 0
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* ret
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* inst64[] for 64 bits:
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* mov rax, 0x02 ; HV_STATUS_INVALID_HYPERCALL_CODE
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* ret
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*/
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const uint8_t inst32[11] = {0xb8U, 0x02U, 0x0U, 0x0U, 0x0U, 0xbaU, 0x0U, 0x0U, 0x0U, 0x0U, 0xc3U};
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const uint8_t inst64[8] = {0x48U, 0xc7U, 0xc0U, 0x02U, 0x0U, 0x0U, 0x0U, 0xc3U};
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hypercall.val64 = val;
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if (hypercall.enabled != 0UL) {
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page_gpa = hypercall.gpfn << PAGE_SHIFT;
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page_hva = gpa2hva(vcpu->vm, page_gpa);
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if (page_hva != NULL) {
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stac();
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(void)memset(page_hva, 0U, PAGE_SIZE);
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if (get_vcpu_mode(vcpu) == CPU_MODE_64BIT) {
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(void)memcpy_s(page_hva, 8U, inst64, 8U);
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} else {
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(void)memcpy_s(page_hva, 11U, inst32, 11U);
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}
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clac();
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}
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}
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}
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int32_t
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hyperv_wrmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t wval)
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{
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int32_t ret = 0;
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switch (msr) {
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case HV_X64_MSR_GUEST_OS_ID:
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vcpu->vm->arch_vm.hyperv.guest_os_id.val64 = wval;
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if (wval == 0UL) {
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vcpu->vm->arch_vm.hyperv.hypercall_page.enabled = 0UL;
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}
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break;
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case HV_X64_MSR_HYPERCALL:
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if (vcpu->vm->arch_vm.hyperv.guest_os_id.val64 == 0UL) {
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pr_warn("hv: %s: guest_os_id is 0", __func__);
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break;
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}
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vcpu->vm->arch_vm.hyperv.hypercall_page.val64 = wval;
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hyperv_setup_hypercall_page(vcpu, wval);
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break;
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case HV_X64_MSR_REFERENCE_TSC:
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hyperv_setup_tsc_page(vcpu, wval);
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break;
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case HV_X64_MSR_VP_INDEX:
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case HV_X64_MSR_TIME_REF_COUNT:
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/* read only */
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/* fallthrough */
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default:
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pr_err("hv: %s: unexpected MSR[0x%x] write", __func__, msr);
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ret = -1;
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break;
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}
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dev_dbg(DBG_LEVEL_HYPERV, "hv: %s: MSR=0x%x wval=0x%lx vcpuid=%d vmid=%d",
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__func__, msr, wval, vcpu->vcpu_id, vcpu->vm->vm_id);
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return ret;
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}
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int32_t
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hyperv_rdmsr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *rval)
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{
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int32_t ret = 0;
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switch (msr) {
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case HV_X64_MSR_GUEST_OS_ID:
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*rval = vcpu->vm->arch_vm.hyperv.guest_os_id.val64;
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break;
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case HV_X64_MSR_HYPERCALL:
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*rval = vcpu->vm->arch_vm.hyperv.hypercall_page.val64;
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break;
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case HV_X64_MSR_VP_INDEX:
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*rval = vcpu->vcpu_id;
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break;
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case HV_X64_MSR_TIME_REF_COUNT:
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*rval = hyperv_get_ReferenceTime(vcpu->vm);
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break;
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case HV_X64_MSR_REFERENCE_TSC:
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*rval = vcpu->vm->arch_vm.hyperv.ref_tsc_page.val64;
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break;
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default:
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pr_err("hv: %s: unexpected MSR[0x%x] read", __func__, msr);
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ret = -1;
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break;
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}
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dev_dbg(DBG_LEVEL_HYPERV, "hv: %s: MSR=0x%x rval=0x%lx vcpuid=%d vmid=%d",
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__func__, msr, *rval, vcpu->vcpu_id, vcpu->vm->vm_id);
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return ret;
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}
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void
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hyperv_init_time(struct acrn_vm *vm)
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{
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uint64_t tsc_scale, tsc_khz = get_tsc_khz();
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uint64_t tsc_offset;
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/*
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* The partition reference time is computed by the following formula:
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* ReferenceTime = ((VirtualTsc * TscScale) >> 64) + TscOffset
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* ReferenceTime is in 100ns units
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*
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* ReferenceTime =
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* VirtualTsc / (get_tsc_khz() * 1000) * 1000000000 / 100
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* + TscOffset
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*
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* TscScale = (10000U << 64U) / get_tsc_khz()
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*/
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tsc_scale = u64_shl64_div_u64(10000U, tsc_khz);
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tsc_offset = hyperv_scale_tsc(tsc_scale);
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vm->arch_vm.hyperv.tsc_scale = tsc_scale;
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vm->arch_vm.hyperv.tsc_offset = tsc_offset;
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dev_dbg(DBG_LEVEL_HYPERV, "%s, tsc_scale = 0x%lx, tsc_offset = %ld",
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__func__, tsc_scale, tsc_offset);
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}
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void
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hyperv_init_vcpuid_entry(uint32_t leaf, uint32_t subleaf, uint32_t flags,
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struct vcpuid_entry *entry)
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{
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entry->leaf = leaf;
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entry->subleaf = subleaf;
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entry->flags = flags;
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switch (leaf) {
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case 0x40000001U: /* HV interface version */
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entry->eax = 0x31237648U; /* "Hv#1" */
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entry->ebx = 0U;
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entry->ecx = 0U;
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entry->edx = 0U;
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break;
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case 0x40000002U: /* HV system identity */
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entry->eax = 0U;
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entry->ebx = 0U;
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entry->ecx = 0U;
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entry->edx = 0U;
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break;
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case 0x40000003U: /* HV supported feature */
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entry->eax = CPUID3A_HYPERCALL_MSR | CPUID3A_VP_INDEX_MSR |
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CPUID3A_TIME_REF_COUNT_MSR | CPUID3A_REFERENCE_TSC_MSR;
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entry->ebx = 0U;
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entry->ecx = 0U;
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entry->edx = 0U;
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break;
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case 0x40000004U: /* HV Recommended hypercall usage */
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entry->eax = 0U;
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entry->ebx = 0U;
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entry->ecx = 0U;
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entry->edx = 0U;
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break;
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case 0x40000005U: /* HV Maximum Supported Virtual & logical Processors */
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entry->eax = MAX_VCPUS_PER_VM;
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entry->ebx = 0U;
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entry->ecx = 0U;
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entry->edx = 0U;
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break;
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case 0x40000006U: /* Implementation Hardware Features */
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entry->eax = 0U;
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entry->ebx = 0U;
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entry->ecx = 0U;
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entry->edx = 0U;
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break;
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default:
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/* do nothing */
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break;
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}
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dev_dbg(DBG_LEVEL_HYPERV, "hv: %s: leaf=%x subleaf=%x flags=%x eax=%x ebx=%x ecx=%x edx=%x",
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__func__, leaf, subleaf, flags, entry->eax, entry->ebx, entry->ecx, entry->edx);
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}
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