105 lines
2.0 KiB
C
105 lines
2.0 KiB
C
/*
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* Copyright (C) 2021-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <errno.h>
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#include <stddef.h>
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#include <sys/queue.h>
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#include <stdlib.h>
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#include "pcireg.h"
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#include "pciaccess.h"
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#include "pci_core.h"
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#include "pci_util.h"
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#include "log.h"
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/* find position of specified pci capability register*/
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int pci_find_cap(struct pci_device *pdev, const int cap_id)
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{
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uint8_t cap_pos, cap_data;
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uint16_t status = 0;
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pci_device_cfg_read_u16(pdev, &status, PCIR_STATUS);
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if (status & PCIM_STATUS_CAPPRESENT) {
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pci_device_cfg_read_u8(pdev, &cap_pos, PCIR_CAP_PTR);
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while (cap_pos != 0 && cap_pos != 0xff) {
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pci_device_cfg_read_u8(pdev, &cap_data,
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cap_pos + PCICAP_ID);
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if (cap_data == cap_id)
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return cap_pos;
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pci_device_cfg_read_u8(pdev, &cap_pos,
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cap_pos + PCICAP_NEXTPTR);
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}
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}
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return 0;
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}
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/* find extend capability register position from cap_id */
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int pci_find_ext_cap(struct pci_device *pdev, int cap_id)
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{
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int offset = 0;
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uint32_t data = 0;
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offset = PCIR_EXTCAP;
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do {
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/* PCI Express Extended Capability must have 4 bytes header */
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pci_device_cfg_read_u32(pdev, &data, offset);
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if (PCI_EXTCAP_ID(data) == cap_id)
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break;
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offset = PCI_EXTCAP_NEXTPTR(data);
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} while (offset != 0);
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return offset;
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}
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/* find pci-e device type */
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int pci_get_pcie_type(struct pci_device *dev)
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{
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uint8_t data = 0;
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int pcie_type;
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int pos = 0;
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if (dev == NULL)
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return -EINVAL;
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pos = pci_find_cap(dev, PCIY_EXPRESS);
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if (!pos)
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return -EINVAL;
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pci_device_cfg_read_u8(dev, &data, pos + PCIER_FLAGS);
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pcie_type = data & PCIEM_FLAGS_TYPE;
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return pcie_type;
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}
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/* check whether pdev is a pci root port */
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bool is_root_port(struct pci_device *pdev)
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{
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int pcie_type;
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pcie_type = pci_get_pcie_type(pdev);
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return (pcie_type == PCIEM_TYPE_ROOT_PORT);
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}
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/* check whether pdev is multi-function device */
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bool is_mfdev(struct pci_device *pdev)
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{
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uint8_t hdr_type;
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pci_device_cfg_read_u8(pdev, &hdr_type, PCIR_HDRTYPE);
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return ((hdr_type & PCIM_MFDEV) == PCIM_MFDEV);
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}
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