73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RTCT_H
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#define RTCT_H
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#define RTCT_ENTRY_TYPE_PTCD_LIMIT 1U
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#define RTCT_ENTRY_TYPE_PTCM_BINARY 2U
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#define RTCT_ENTRY_TYPE_WRC_L3_MASKS 3U
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#define RTCT_ENTRY_TYPE_GT_L3_MASKS 4U
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#define RTCT_ENTRY_TYPE_SSRAM 5U
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#define RTCT_ENTRY_TYPE_STREAM_DATAPATH 6U
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#define RTCT_ENTRY_TYPE_TIMEAWARE_SUBSYS 7U
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#define RTCT_ENTRY_TYPE_RT_IOMMU 8U
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#define RTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
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/*Entry IDs for RTCT version 2*/
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#define RTCT_V2_COMPATIBILITY 0U
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#define RTCT_V2_RTCD_LIMIT 1U
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#define RTCT_V2_CRL_BINARY 2U
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#define RTCT_V2_IA_WAYMASK 3U
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#define RTCT_V2_WRC_WAYMASK 4U
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#define RTCT_V2_GT_WAYMASK 5U
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#define RTCT_V2_SSRAM_WAYMASK 6U
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#define RTCT_V2_SSRAM 7U
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#define RTCT_V2_MEMORY_HIERARCHY_LATENCY 8U
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#define RTCT_V2_ERROR_LOG_ADDRESS 9U
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struct rtct_entry {
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uint16_t size;
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uint16_t format_version;
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uint32_t type;
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uint32_t data[64];
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} __packed;
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struct rtct_entry_data_compatibility {
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uint32_t RTCT_Ver_Major;
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uint32_t RTCT_Ver_Minor;
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uint32_t RTCD_Ver_Major;
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uint32_t RTCD_Ver_Minor;
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} __packed;
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struct rtct_entry_data_ssram {
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uint32_t cache_level;
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uint64_t base;
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uint32_t ways;
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uint32_t size;
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uint32_t apic_id_tbl[64];
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} __packed;
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struct rtct_entry_data_ssram_v2 {
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uint32_t cache_level;
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uint32_t cache_id;
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uint64_t base;
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uint32_t size;
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uint32_t shared;
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} __packed;
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struct rtct_entry_data_mem_hi_latency {
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uint32_t hierarchy;
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uint32_t clock_cycles;
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uint32_t apic_id_tbl[64];
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} __packed;
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uint64_t get_software_sram_base_hpa(void);
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uint64_t get_software_sram_size(void);
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uint8_t *build_vrtct(struct vmctx *ctx, void *cfg);
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#endif /* RTCT_H */
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