296 lines
8.1 KiB
C
296 lines
8.1 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PTDEV_H
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#define PTDEV_H
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#include <list.h>
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#include <asm/lib/spinlock.h>
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#include <timer.h>
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#include <vacpi.h>
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enum intx_ctlr {
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INTX_CTLR_IOAPIC = 0U,
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INTX_CTLR_PIC
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};
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#define PTDEV_INTR_MSI (1U << 0U)
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#define PTDEV_INTR_INTX (1U << 1U)
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#define GPU_OPREGION_SIZE 0x5000U
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#define GPU_OPREGION_GPA (VIRT_ACPI_DATA_ADDR - GPU_OPREGION_SIZE)
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#define PCIR_ASLS_CTL 0xfcU /* register offset in PCIe configuration space for Opregion base address */
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#define PCIM_ASLS_OPREGION_MASK 0xfffff000U /* opregion need 4KB aligned */
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#define INVALID_PTDEV_ENTRY_ID 0xffffU
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#define DEFINE_MSI_SID(name, a, b) \
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union source_id (name) = {.msi_id = {.bdf = (a), .entry_nr = (b)} }
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#define DEFINE_INTX_SID(name, a, b) \
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union source_id (name) = {.intx_id = {.gsi = (a), .ctlr = (b)} }
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union irte_index {
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uint16_t index;
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struct {
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uint16_t index_low:15;
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uint16_t index_high:1;
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} bits __packed;
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};
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union source_id {
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uint64_t value;
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struct {
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uint16_t bdf;
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uint16_t entry_nr;
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uint32_t reserved;
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} msi_id;
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/*
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* ctlr indicates if the source of interrupt is IO-APIC or PIC
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* pin indicates the pin number of interrupt controller determined by ctlr
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*/
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struct {
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enum intx_ctlr ctlr;
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uint32_t gsi;
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} intx_id;
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};
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/*
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* Macros for bits in union msi_addr_reg
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*/
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#define MSI_ADDR_BASE 0xfeeUL /* Base address for MSI messages */
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#define MSI_ADDR_RH 0x1U /* Redirection Hint */
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#define MSI_ADDR_DESTMODE_LOGICAL 0x1U /* Destination Mode: Logical*/
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#define MSI_ADDR_DESTMODE_PHYS 0x0U /* Destination Mode: Physical*/
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union msi_addr_reg {
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uint64_t full;
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struct {
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uint32_t rsvd_1:2;
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uint32_t dest_mode:1;
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uint32_t rh:1;
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uint32_t rsvd_2:8;
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uint32_t dest_field:8;
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uint32_t addr_base:12;
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uint32_t hi_32;
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} bits __packed;
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struct {
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uint32_t rsvd_1:2;
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uint32_t intr_index_high:1;
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uint32_t shv:1;
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uint32_t intr_format:1;
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uint32_t intr_index_low:15;
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uint32_t constant:12;
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uint32_t hi_32;
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} ir_bits __packed;
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};
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/*
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* Macros for bits in union msi_data_reg
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*/
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#define MSI_DATA_DELMODE_FIXED 0x0U /* Delivery Mode: Fixed */
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#define MSI_DATA_DELMODE_LOPRI 0x1U /* Delivery Mode: Low Priority */
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#define MSI_DATA_TRGRMODE_EDGE 0x0U /* Trigger Mode: Edge */
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#define MSI_DATA_TRGRMODE_LEVEL 0x1U /* Trigger Mode: Level */
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union msi_data_reg {
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uint32_t full;
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struct {
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uint32_t vector:8;
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uint32_t delivery_mode:3;
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uint32_t rsvd_1:3;
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uint32_t level:1;
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uint32_t trigger_mode:1;
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uint32_t rsvd_2:16;
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} bits __packed;
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};
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struct msi_info {
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union msi_addr_reg addr;
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union msi_data_reg data;
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};
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struct ptirq_remapping_info;
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typedef void (*ptirq_arch_release_fn_t)(const struct ptirq_remapping_info *entry);
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/* entry per each allocated irq/vector
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* it represents a pass-thru device's remapping data entry which collecting
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* information related with its vm and msi/intx mapping & interaction nodes
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* with interrupt handler and softirq.
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*/
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struct ptirq_remapping_info {
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struct hlist_node phys_link;
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struct hlist_node virt_link;
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uint16_t ptdev_entry_id;
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uint32_t intr_type;
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union source_id phys_sid;
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union source_id virt_sid;
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struct acrn_vm *vm;
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bool active; /* true=active, false=inactive*/
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uint32_t allocated_pirq;
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uint32_t polarity; /* 0=active high, 1=active low*/
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struct list_head softirq_node;
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struct msi_info vmsi;
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struct msi_info pmsi;
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uint16_t irte_idx;
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uint64_t intr_count;
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struct hv_timer intr_delay_timer; /* used for delay intr injection */
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ptirq_arch_release_fn_t release_cb;
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};
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static inline bool is_entry_active(const struct ptirq_remapping_info *entry)
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{
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return entry->active;
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}
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extern struct ptirq_remapping_info ptirq_entries[CONFIG_MAX_PT_IRQ_ENTRIES];
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extern spinlock_t ptdev_lock;
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/**
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* @file ptdev.h
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*
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* @brief public APIs for ptdev
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*/
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/**
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* @brief ptdev
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*
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* @addtogroup acrn_passthrough
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* @{
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*/
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/*
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* @brief Find a ptdev entry by sid
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*
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* param[in] intr_type interrupt type of the ptirq entry
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* param[in] sid source id of the ptirq entry
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* param[in] vm vm pointer of the ptirq entry if find the ptdev entry by virtual sid
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*
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* @retval NULL when no ptirq entry match the sid
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* @retval ptirq entry when there is available ptirq entry match the sid
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*
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* @pre: vm must be NULL when lookup by physical sid, otherwise,
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* vm must not be NULL when lookup by virtual sid.
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*/
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struct ptirq_remapping_info *find_ptirq_entry(uint32_t intr_type,
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const union source_id *sid, const struct acrn_vm *vm);
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/**
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* @brief Handler of softirq for passthrough device.
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*
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* When hypervisor receive a physical interrupt from passthrough device, it
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* will enqueue a ptirq entry and raise softirq SOFTIRQ_PTDEV. This function
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* is the handler of the softirq, it handles the interrupt and injects the
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* virtual into VM.
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* The handler is registered by calling @ref ptdev_init during hypervisor
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* initialization.
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*
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* @param[in] pcpu_id physical cpu id of the soft irq
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*
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*/
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void ptirq_softirq(uint16_t pcpu_id);
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/**
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* @brief Passthrough device global data structure initialization.
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*
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* During the hypervisor cpu initialization stage, this function:
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* - init global spinlock for ptdev (on BSP)
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* - register SOFTIRQ_PTDEV handler (on BSP)
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* - init the softirq entry list for each CPU
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*
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*/
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void ptdev_init(void);
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/**
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* @brief Deactivate and release all ptirq entries for a VM.
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*
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* This function deactivates and releases all ptirq entries for a VM. The function
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* should only be called after the VM is already down.
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*
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* @param[in] vm acrn_vm on which the ptirq entries will be released
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*
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* @pre VM is already down
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*
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*/
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void ptdev_release_all_entries(const struct acrn_vm *vm);
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/**
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* @brief Dequeue an entry from per cpu ptdev softirq queue.
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*
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* Dequeue an entry from the ptdev softirq queue on the specific physical cpu.
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*
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* @param[in] pcpu_id physical cpu id
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*
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* @retval NULL when the queue is empty
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* @retval !NULL when there is available ptirq_remapping_info entry in the queue
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*
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*/
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struct ptirq_remapping_info *ptirq_dequeue_softirq(uint16_t pcpu_id);
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/**
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* @brief Allocate a ptirq_remapping_info entry.
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*
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* Allocate a ptirq_remapping_info entry for hypervisor to store the remapping information.
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* The total number of the entries is statically defined as CONFIG_MAX_PT_IRQ_ENTRIES.
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* Appropriate number should be configured on different platforms.
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*
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* @param[in] vm acrn_vm that the entry allocated for.
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* @param[in] intr_type interrupt type: PTDEV_INTR_MSI or PTDEV_INTR_INTX
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*
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* @retval NULL when the number of entries allocated is CONFIG_MAX_PT_IRQ_ENTRIES
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* @retval !NULL when the number of entries allocated is less than CONFIG_MAX_PT_IRQ_ENTRIES
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*
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*/
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struct ptirq_remapping_info *ptirq_alloc_entry(struct acrn_vm *vm, uint32_t intr_type);
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/**
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* @brief Release a ptirq_remapping_info entry.
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*
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* @param[in] entry the ptirq_remapping_info entry to release.
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*
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*/
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void ptirq_release_entry(struct ptirq_remapping_info *entry);
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/**
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* @brief Activate a irq for the associated passthrough device.
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*
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* After activating the ptirq entry, the physical interrupt irq of passthrough device will be handled
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* by the handler ptirq_interrupt_handler.
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*
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* @param[in] entry the ptirq_remapping_info entry that will be associated with the physical irq.
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* @param[in] phys_irq physical interrupt irq for the entry
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*
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* @retval success when return value >=0
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* @retval failure when return value < 0
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*
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*/
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int32_t ptirq_activate_entry(struct ptirq_remapping_info *entry, uint32_t phys_irq);
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/**
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* @brief De-activate a irq for the associated passthrough device.
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*
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* @param[in] entry the ptirq_remapping_info entry that will be de-activated.
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*
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*/
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void ptirq_deactivate_entry(struct ptirq_remapping_info *entry);
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/**
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* @brief Get the interrupt information and store to the buffer provided.
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*
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* @param[in] target_vm the VM to get the interrupt information.
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* @param[out] buffer where interrupt information is stored.
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* @param[in] buffer_cnt the size of the buffer.
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*
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* @retval the actual size the buffer filled with the interrupt information
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*
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*/
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uint32_t ptirq_get_intr_data(const struct acrn_vm *target_vm, uint64_t *buffer, uint32_t buffer_cnt);
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/**
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* @}
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*/
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#endif /* PTDEV_H */
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