229 lines
6.2 KiB
C
229 lines
6.2 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <asm/cpu.h>
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#include <asm/cpu_caps.h>
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#include <asm/cpufeatures.h>
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#include <asm/cpuid.h>
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#include <errno.h>
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#include <logmsg.h>
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#include <asm/rdt.h>
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#include <asm/lib/bits.h>
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#include <asm/board.h>
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#include <asm/vm_config.h>
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#include <asm/msr.h>
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const uint16_t hv_clos = 0U;
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/* RDT features can support different numbers of CLOS. Set the lowers numerical
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* clos value (valid_clos_num) that is common between the resources as
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* each resource's clos max value to have consistent allocation.
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*/
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#ifdef CONFIG_RDT_ENABLED
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uint16_t valid_clos_num = HV_SUPPORTED_MAX_CLOS;
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static struct rdt_info res_cap_info[RDT_NUM_RESOURCES] = {
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[RDT_RESOURCE_L3] = {
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.res.cache = {
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.bitmask = 0U,
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.cbm_len = 0U,
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.msr_qos_cfg = MSR_IA32_L3_QOS_CFG,
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},
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.clos_max = 0U,
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.res_id = RDT_RESID_L3,
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.msr_base = MSR_IA32_L3_MASK_BASE,
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.platform_clos_array = platform_l3_clos_array,
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},
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[RDT_RESOURCE_L2] = {
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.res.cache = {
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.bitmask = 0U,
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.cbm_len = 0U,
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.msr_qos_cfg = MSR_IA32_L2_QOS_CFG,
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},
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.clos_max = 0U,
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.res_id = RDT_RESID_L2,
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.msr_base = MSR_IA32_L2_MASK_BASE,
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.platform_clos_array = platform_l2_clos_array,
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},
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[RDT_RESOURCE_MBA] = {
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.res.membw = {
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.mba_max = 0U,
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.delay_linear = true,
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},
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.clos_max = 0U,
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.res_id = RDT_RESID_MBA,
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.msr_base = MSR_IA32_MBA_MASK_BASE,
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.platform_clos_array = platform_mba_clos_array,
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},
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};
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/*
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* @pre res == RDT_RESOURCE_L3 || res == RDT_RESOURCE_L2
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*/
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static void init_cat_capability(int res)
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{
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uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
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/* CPUID.(EAX=0x10,ECX=ResID):EAX[4:0] reports the length of CBM supported
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* CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] indicates shared cache mask bits
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* that are used by other entities such as graphic and H/W outside processor.
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* CPUID.(EAX=0x10,ECX=ResID):EDX[15:0] reports the maximun CLOS supported
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*/
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cpuid_subleaf(CPUID_RDT_ALLOCATION, res_cap_info[res].res_id, &eax, &ebx, &ecx, &edx);
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res_cap_info[res].res.cache.cbm_len = (uint16_t)((eax & 0x1fU) + 1U);
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res_cap_info[res].res.cache.bitmask = ebx;
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#ifdef CONFIG_CDP_ENABLED
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res_cap_info[res].res.cache.is_cdp_enabled = ((ecx & 0x4U) != 0U);
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#else
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res_cap_info[res].res.cache.is_cdp_enabled = false;
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#endif
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if (res_cap_info[res].res.cache.is_cdp_enabled) {
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res_cap_info[res].clos_max = (uint16_t)((edx & 0xffffU) >> 1U) + 1U;
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/* enable CDP before setting COS to simplify CAT mask remapping
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* and prevent unintended behavior.
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*/
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msr_write(res_cap_info[res].res.cache.msr_qos_cfg, 0x1UL);
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} else {
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res_cap_info[res].clos_max = (uint16_t)(edx & 0xffffU) + 1U;
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}
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}
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static void init_mba_capability(int res)
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{
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uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
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/* CPUID.(EAX=0x10,ECX=ResID):EAX[11:0] reports maximum MBA throttling value supported
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* CPUID.(EAX=0x10,ECX=ResID):EBX[31:0] reserved
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* CPUID.(EAX=10H, ECX=ResID=3):ECX[2] reports if response of the delay values is linear
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* CPUID.(EAX=0x10,ECX=ResID):EDX[15:0] reports the maximun CLOS supported
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*/
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cpuid_subleaf(CPUID_RDT_ALLOCATION, res_cap_info[res].res_id, &eax, &ebx, &ecx, &edx);
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res_cap_info[res].res.membw.mba_max = (uint16_t)((eax & 0xfffU) + 1U);
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res_cap_info[res].res.membw.delay_linear = ((ecx & 0x4U) != 0U);
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res_cap_info[res].clos_max = (uint16_t)(edx & 0xffffU) + 1U;
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}
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/*
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* @pre valid_clos_num > 0U
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*/
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void init_rdt_info(void)
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{
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uint8_t i;
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uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U;
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if (pcpu_has_cap(X86_FEATURE_RDT_A)) {
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cpuid_subleaf(CPUID_RDT_ALLOCATION, 0U, &eax, &ebx, &ecx, &edx);
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/* If HW supports L3 CAT, EBX[1] is set */
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if ((ebx & 2U) != 0U) {
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init_cat_capability(RDT_RESOURCE_L3);
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}
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/* If HW supports L2 CAT, EBX[2] is set */
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if ((ebx & 4U) != 0U) {
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init_cat_capability(RDT_RESOURCE_L2);
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}
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/* If HW supports MBA, EBX[3] is set */
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if ((ebx & 8U) != 0U) {
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init_mba_capability(RDT_RESOURCE_MBA);
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}
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for (i = 0U; i < RDT_NUM_RESOURCES; i++) {
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/* If clos_max == 0, the resource is not supported. Set the
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* valid_clos_num as the minimal clos_max of all support rdt resource.
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*/
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if (res_cap_info[i].clos_max > 0U) {
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if (res_cap_info[i].clos_max < valid_clos_num) {
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valid_clos_num = res_cap_info[i].clos_max;
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}
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}
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}
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}
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}
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/*
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* @pre res < RDT_NUM_RESOURCES
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* @pre res_clos_info[i].mba_delay <= res_cap_info[res].res.membw.mba_max
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* @pre length of res_clos_info[i].clos_mask <= cbm_len && all 1's in clos_mask is continuous
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*/
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static void setup_res_clos_msr(uint16_t pcpu_id, uint16_t res, struct platform_clos_info *res_clos_info)
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{
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uint16_t i, mask_array_size = valid_clos_num;
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uint32_t msr_index;
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uint64_t val;
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if (res != RDT_RESOURCE_MBA && res_cap_info[res].res.cache.is_cdp_enabled) {
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mask_array_size = mask_array_size << 1U;
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}
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for (i = 0U; i < mask_array_size; i++) {
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switch (res) {
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case RDT_RESOURCE_L3:
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case RDT_RESOURCE_L2:
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val = (uint64_t)res_clos_info[i].value.clos_mask;
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break;
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case RDT_RESOURCE_MBA:
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val = (uint64_t)res_clos_info[i].value.mba_delay;
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break;
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default:
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ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res);
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}
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msr_index = res_cap_info[res].msr_base + i;
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msr_write_pcpu(msr_index, val, pcpu_id);
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}
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}
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void setup_clos(uint16_t pcpu_id)
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{
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uint16_t i;
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for (i = 0U; i < RDT_NUM_RESOURCES; i++) {
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/* If clos_max == 0, the resource is not supported
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* so skip setting up resource MSR.
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*/
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if (res_cap_info[i].clos_max > 0U) {
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setup_res_clos_msr(pcpu_id, i, res_cap_info[i].platform_clos_array);
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}
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}
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/* set hypervisor RDT resource clos */
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msr_write_pcpu(MSR_IA32_PQR_ASSOC, clos2pqr_msr(hv_clos), pcpu_id);
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}
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uint64_t clos2pqr_msr(uint16_t clos)
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{
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uint64_t pqr_assoc;
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pqr_assoc = msr_read(MSR_IA32_PQR_ASSOC);
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pqr_assoc = (pqr_assoc & 0xffffffffUL) | ((uint64_t)clos << 32U);
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return pqr_assoc;
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}
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bool is_platform_rdt_capable(void)
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{
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bool ret = false;
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if ((res_cap_info[RDT_RESOURCE_L3].clos_max > 0U) ||
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(res_cap_info[RDT_RESOURCE_L2].clos_max > 0U) ||
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(res_cap_info[RDT_RESOURCE_MBA].clos_max > 0U)) {
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ret = true;
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}
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return ret;
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}
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#else
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uint64_t clos2pqr_msr(__unused uint16_t clos)
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{
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return 0UL;
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}
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bool is_platform_rdt_capable(void)
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{
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return false;
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}
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#endif
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