255 lines
6.7 KiB
ArmAsm
255 lines
6.7 KiB
ArmAsm
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <vmx.h>
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#include <msr.h>
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#include <guest.h>
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#include <vcpu.h>
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#include <cpu.h>
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#include <types.h>
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/* NOTE:
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*
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* MISRA C requires that all unsigned constants should have the suffix 'U'
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* (e.g. 0xffU), but the assembler may not accept such C-style constants. For
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* example, binutils 2.26 fails to compile assembly in that case. To work this
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* around, all unsigned constants must be explicitly spells out in assembly
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* with a comment tracking the original expression from which the magic
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* number is calculated. As an example:
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*
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* /* 0x00000668 =
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* * (CR4_DE | CR4_PAE | CR4_MCE | CR4_OSFXSR | CR4_OSXMMEXCPT) *\/
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* movl $0x00000668, %eax
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*
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* Make sure that these numbers are updated accordingly if the definition of
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* the macros involved are changed.
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*/
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.text
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/*int vmx_vmrun(struct run_context *context, int launch, int ibrs_type) */
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.code64
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.align 8
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.global vmx_vmrun
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vmx_vmrun:
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/* Save all host GPRs that must be preserved across function calls
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per System V ABI */
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push %rdx
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push %rbx
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push %rbp
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push %r12
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push %r13
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push %r14
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push %r15
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/* Save RDI on top of host stack for easy access to VCPU pointer
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on return from guest context */
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push %rdi
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/* rdx = ibrs_type */
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/* if ibrs_type != IBRS_NONE, means IBRS feature is supported,
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* restore MSR SPEC_CTRL to guest
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*/
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cmp $IBRS_NONE,%rdx
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je next
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/* 0x00000048 = MSR_IA32_SPEC_CTRL */
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movl $0x00000048,%ecx
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mov CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rdi),%rax
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movl $0,%edx
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wrmsr
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next:
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/* Load VMCS_HOST_RSP_FIELD field value
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*
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* 0x00006c14 = VMX_HOST_RSP
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*/
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mov $0x00006c14,%rdx
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/* Write the current stack pointer to the VMCS_HOST_RSP_FIELD */
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vmwrite %rsp,%rdx
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/* Error occurred - handle error */
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jbe vm_eval_error
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/* Compare the launch flag to see if launching (1) or resuming (0) */
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cmp $VM_LAUNCH, %rsi
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mov CPU_CONTEXT_OFFSET_CR2(%rdi),%rax
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mov %rax,%cr2
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mov CPU_CONTEXT_OFFSET_RAX(%rdi),%rax
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mov CPU_CONTEXT_OFFSET_RBX(%rdi),%rbx
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mov CPU_CONTEXT_OFFSET_RCX(%rdi),%rcx
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mov CPU_CONTEXT_OFFSET_RDX(%rdi),%rdx
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mov CPU_CONTEXT_OFFSET_RBP(%rdi),%rbp
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mov CPU_CONTEXT_OFFSET_RSI(%rdi),%rsi
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mov CPU_CONTEXT_OFFSET_R8(%rdi),%r8
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mov CPU_CONTEXT_OFFSET_R9(%rdi),%r9
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mov CPU_CONTEXT_OFFSET_R10(%rdi),%r10
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mov CPU_CONTEXT_OFFSET_R11(%rdi),%r11
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mov CPU_CONTEXT_OFFSET_R12(%rdi),%r12
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mov CPU_CONTEXT_OFFSET_R13(%rdi),%r13
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mov CPU_CONTEXT_OFFSET_R14(%rdi),%r14
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mov CPU_CONTEXT_OFFSET_R15(%rdi),%r15
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mov CPU_CONTEXT_OFFSET_RDI(%rdi),%rdi
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/* Execute appropriate VMX instruction */
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je vm_launch
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/* Execute a VM resume */
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vmresume
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/* jump to vm_exit directly when it fails in vmresume */
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jmp vm_exit
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vm_launch:
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/* Execute a VM launch */
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vmlaunch
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.global vm_exit
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vm_exit:
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/* Get VCPU data structure pointer from top of host stack and
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save guest RDI in its place */
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xchg 0(%rsp),%rdi
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/* Save current GPRs to guest state area */
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mov %rax,CPU_CONTEXT_OFFSET_RAX(%rdi)
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mov %cr2,%rax
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mov %rax,CPU_CONTEXT_OFFSET_CR2(%rdi)
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mov %rbx,CPU_CONTEXT_OFFSET_RBX(%rdi)
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mov %rcx,CPU_CONTEXT_OFFSET_RCX(%rdi)
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mov %rdx,CPU_CONTEXT_OFFSET_RDX(%rdi)
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mov %rbp,CPU_CONTEXT_OFFSET_RBP(%rdi)
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mov %rsi,CPU_CONTEXT_OFFSET_RSI(%rdi)
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mov %r8,CPU_CONTEXT_OFFSET_R8(%rdi)
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mov %r9,CPU_CONTEXT_OFFSET_R9(%rdi)
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mov %r10,CPU_CONTEXT_OFFSET_R10(%rdi)
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mov %r11,CPU_CONTEXT_OFFSET_R11(%rdi)
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mov %r12,CPU_CONTEXT_OFFSET_R12(%rdi)
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mov %r13,CPU_CONTEXT_OFFSET_R13(%rdi)
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mov %r14,CPU_CONTEXT_OFFSET_R14(%rdi)
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mov %r15,CPU_CONTEXT_OFFSET_R15(%rdi)
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/* Load guest RDI off host stack and into RDX */
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mov 0(%rsp),%rdx
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/* Save guest RDI to guest state area */
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mov %rdx,CPU_CONTEXT_OFFSET_RDI(%rdi)
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/* Save RDI to RSI for later SPEC_CTRL save*/
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mov %rdi,%rsi
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vm_eval_error:
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/* Restore host GPR System V required registers */
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pop %rdi
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pop %r15
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pop %r14
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pop %r13
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pop %r12
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pop %rbp
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pop %rbx
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pop %rdx
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/* Check vm fail, refer to 64-ia32 spec section 26.2 in volume#3 */
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mov $VM_FAIL,%rax
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jc vm_return
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jz vm_return
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/* Clear host registers to prevent speculative use */
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xor %rcx,%rcx
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xor %r8,%r8
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xor %r9,%r9
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xor %r10,%r10
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xor %r11,%r11
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/* rdx = ibrs_type */
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/* IBRS_NONE: no ibrs setting, just flush rsb
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* IBRS_RAW: set IBRS then flush rsb
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* IBRS_OPT: set STIBP & IBPB then flush rsb
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*/
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cmp $IBRS_NONE,%rdx
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je stuff_rsb
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cmp $IBRS_OPT,%rdx
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je ibrs_opt
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/* Save guest MSR SPEC_CTRL, low 32 bit is enough
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*
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* 0x00000048 = MSR_IA32_SPEC_CTRL
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*/
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movl $0x00000048,%ecx
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rdmsr
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mov %rax,CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rsi)
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/* 0x1 = SPEC_ENABLE_IBRS */
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movl $0x1,%eax
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movl $0,%edx
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wrmsr
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jmp stuff_rsb
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ibrs_opt:
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/* 0x00000049 = MSR_IA32_PRED_CMD */
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movl $0x00000049,%ecx
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/* 0x1 = PRED_SET_IBPB */
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movl $0x1,%eax
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movl $0,%edx
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wrmsr
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/* Save guest MSR SPEC_CTRL, low 32 bit is enough
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*
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* 0x00000048 = MSR_IA32_SPEC_CTRL
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*/
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movl $0x00000048,%ecx
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rdmsr
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mov %rax,CPU_CONTEXT_OFFSET_IA32_SPEC_CTRL(%rsi)
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/* 0x2 = SPEC_ENABLE_STIBP */
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movl $0x2,%eax
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movl $0,%edx
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wrmsr
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/* stuff rsb by 32 CALLs, make sure no any "ret" is executed before this
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* stuffing rsb, otherwise, someone may insert some code before this for
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* future update.
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*/
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stuff_rsb:
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/* stuff 32 RSB, rax = 32/2 */
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mov $16,%rax
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.align 16
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3:
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call 4f
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33:
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pause
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jmp 33b
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.align 16
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4:
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call 5f
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44:
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pause
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jmp 44b
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.align 16
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5: dec %rax
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jnz 3b
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/* stuff 32 RSB, rsp += 8*32 */
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add $(8*32),%rsp
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mov $VM_SUCCESS,%rax
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vm_return:
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/* Return to caller */
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ret
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