435 lines
13 KiB
C
435 lines
13 KiB
C
/*-
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* Copyright (c) 1996, by Peter Wemm and Steve Passe
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef APICREG_H
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#define APICREG_H
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#include <page.h>
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/*
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* Local && I/O APIC definitions.
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*/
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/******************************************************************************
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* global defines, etc.
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*/
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/******************************************************************************
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* LOCAL APIC structure
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*/
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struct lapic_reg {
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uint32_t v;
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uint32_t pad[3];
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};
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struct lapic_regs { /*OFFSET(Hex)*/
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struct lapic_reg rsv0[2];
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struct lapic_reg id; /*020*/
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struct lapic_reg version; /*030*/
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struct lapic_reg rsv1[4];
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struct lapic_reg tpr; /*080*/
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struct lapic_reg apr; /*090*/
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struct lapic_reg ppr; /*0A0*/
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struct lapic_reg eoi; /*0B0*/
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struct lapic_reg rrd; /*0C0*/
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struct lapic_reg ldr; /*0D0*/
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struct lapic_reg dfr; /*0EO*/
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struct lapic_reg svr; /*0F0*/
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struct lapic_reg isr[8]; /*100 -- 170*/
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struct lapic_reg tmr[8]; /*180 -- 1F0*/
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struct lapic_reg irr[8]; /*200 -- 270*/
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struct lapic_reg esr; /*280*/
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struct lapic_reg rsv2[6];
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struct lapic_reg lvt_cmci; /*2F0*/
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struct lapic_reg icr_lo; /*300*/
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struct lapic_reg icr_hi; /*310*/
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struct lapic_reg lvt[6]; /*320 -- 370*/
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struct lapic_reg icr_timer;/*380*/
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struct lapic_reg ccr_timer;/*390*/
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struct lapic_reg rsv3[4];
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struct lapic_reg dcr_timer;/*3E0*/
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struct lapic_reg self_ipi; /*3F0*/
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/*roundup sizeof current struct to 4KB*/
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struct lapic_reg rsv5[192]; /*400 -- FF0*/
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} __aligned(PAGE_SIZE);
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enum LAPIC_REGISTERS {
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LAPIC_ID = 0x2,
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LAPIC_VERSION = 0x3,
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LAPIC_TPR = 0x8,
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LAPIC_APR = 0x9,
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LAPIC_PPR = 0xa,
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LAPIC_EOI = 0xb,
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LAPIC_LDR = 0xd,
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LAPIC_DFR = 0xe, /* Not in x2APIC */
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LAPIC_SVR = 0xf,
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LAPIC_ISR0 = 0x10,
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LAPIC_ISR1 = 0x11,
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LAPIC_ISR2 = 0x12,
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LAPIC_ISR3 = 0x13,
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LAPIC_ISR4 = 0x14,
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LAPIC_ISR5 = 0x15,
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LAPIC_ISR6 = 0x16,
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LAPIC_ISR7 = 0x17,
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LAPIC_TMR0 = 0x18,
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LAPIC_TMR1 = 0x19,
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LAPIC_TMR2 = 0x1a,
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LAPIC_TMR3 = 0x1b,
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LAPIC_TMR4 = 0x1c,
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LAPIC_TMR5 = 0x1d,
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LAPIC_TMR6 = 0x1e,
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LAPIC_TMR7 = 0x1f,
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LAPIC_IRR0 = 0x20,
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LAPIC_IRR1 = 0x21,
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LAPIC_IRR2 = 0x22,
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LAPIC_IRR3 = 0x23,
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LAPIC_IRR4 = 0x24,
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LAPIC_IRR5 = 0x25,
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LAPIC_IRR6 = 0x26,
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LAPIC_IRR7 = 0x27,
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LAPIC_ESR = 0x28,
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LAPIC_LVT_CMCI = 0x2f,
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LAPIC_ICR_LO = 0x30,
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LAPIC_ICR_HI = 0x31, /* Not in x2APIC */
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LAPIC_LVT_TIMER = 0x32,
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LAPIC_LVT_THERMAL = 0x33,
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LAPIC_LVT_PCINT = 0x34,
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LAPIC_LVT_LINT0 = 0x35,
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LAPIC_LVT_LINT1 = 0x36,
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LAPIC_LVT_ERROR = 0x37,
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LAPIC_ICR_TIMER = 0x38,
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LAPIC_CCR_TIMER = 0x39,
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LAPIC_DCR_TIMER = 0x3e,
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LAPIC_SELF_IPI = 0x3f, /* Only in x2APIC */
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LAPIC_EXT_FEATURES = 0x40, /* AMD */
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LAPIC_EXT_CTRL = 0x41, /* AMD */
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LAPIC_EXT_SEOI = 0x42, /* AMD */
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LAPIC_EXT_IER0 = 0x48, /* AMD */
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LAPIC_EXT_IER1 = 0x49, /* AMD */
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LAPIC_EXT_IER2 = 0x4a, /* AMD */
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LAPIC_EXT_IER3 = 0x4b, /* AMD */
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LAPIC_EXT_IER4 = 0x4c, /* AMD */
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LAPIC_EXT_IER5 = 0x4d, /* AMD */
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LAPIC_EXT_IER6 = 0x4e, /* AMD */
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LAPIC_EXT_IER7 = 0x4f, /* AMD */
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LAPIC_EXT_LVT0 = 0x50, /* AMD */
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LAPIC_EXT_LVT1 = 0x51, /* AMD */
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LAPIC_EXT_LVT2 = 0x52, /* AMD */
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LAPIC_EXT_LVT3 = 0x53, /* AMD */
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};
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#define LAPIC_MEM_MUL 0x10
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/*
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* Although some registers are available on AMD processors only,
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* it's not a big waste to reserve them on all platforms.
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* However, we need to watch out for this space being assigned for
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* non-APIC purposes in the future processor models.
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*/
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#define LAPIC_MEM_REGION ((LAPIC_EXT_LVT3 + 1) * LAPIC_MEM_MUL)
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/******************************************************************************
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* I/O APIC structure
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*/
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struct ioapic {
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uint32_t ioregsel;
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uint32_t rsv0[3];
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uint32_t iowin;
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uint32_t rsv1[3];
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};
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/* IOAPIC Redirection Table (RTE) Entry structure */
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union ioapic_rte {
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uint64_t full;
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struct {
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uint32_t lo_32;
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uint32_t hi_32;
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} u;
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};
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/******************************************************************************
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* various code 'logical' values
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*/
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/******************************************************************************
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* LOCAL APIC defines
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*/
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/* default physical locations of LOCAL (CPU) APICs */
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#define DEFAULT_APIC_BASE 0xfee00000UL
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/* constants relating to APIC ID registers */
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#define APIC_ID_MASK 0xff000000U
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#define APIC_ID_SHIFT 24U
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#define APIC_ID_CLUSTER 0xf0U
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#define APIC_ID_CLUSTER_ID 0x0fU
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#define APIC_MAX_CLUSTER 0xeU
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#define APIC_MAX_INTRACLUSTER_ID 3
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#define APIC_ID_CLUSTER_SHIFT 4
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/* fields in VER */
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#define APIC_VER_VERSION 0x000000ffU
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#define APIC_VER_MAXLVT 0x00ff0000U
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#define MAXLVTSHIFT 16U
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#define APIC_VER_EOI_SUPPRESSION 0x01000000U
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#define APIC_VER_AMD_EXT_SPACE 0x80000000U
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/* fields in LDR */
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#define APIC_LDR_RESERVED 0x00ffffffU
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/* fields in DFR */
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#define APIC_DFR_RESERVED 0x0fffffffU
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#define APIC_DFR_MODEL_MASK 0xf0000000U
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#define APIC_DFR_MODEL_FLAT 0xf0000000U
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#define APIC_DFR_MODEL_CLUSTER 0x00000000U
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/* fields in SVR */
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#define APIC_SVR_VECTOR 0x000000ffU
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#define APIC_SVR_VEC_PROG 0x000000f0U
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#define APIC_SVR_VEC_FIX 0x0000000fU
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#define APIC_SVR_ENABLE 0x00000100U
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#define APIC_SVR_SWDIS 0x00000000U
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#define APIC_SVR_SWEN 0x00000100U
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#define APIC_SVR_FOCUS 0x00000200U
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#define APIC_SVR_FEN 0x00000000U
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#define APIC_SVR_FDIS 0x00000200U
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#define APIC_SVR_EOI_SUPPRESSION 0x00001000U
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/* fields in TPR */
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#define APIC_TPR_PRIO 0x000000ffU
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#define APIC_TPR_INT 0x000000f0U
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#define APIC_TPR_SUB 0x0000000fU
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/* fields in ESR */
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#define APIC_ESR_SEND_CS_ERROR 0x00000001U
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#define APIC_ESR_RECEIVE_CS_ERROR 0x00000002U
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#define APIC_ESR_SEND_ACCEPT 0x00000004U
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#define APIC_ESR_RECEIVE_ACCEPT 0x00000008U
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#define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020U
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#define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040U
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#define APIC_ESR_ILLEGAL_REGISTER 0x00000080U
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/* fields in ICR_LOW */
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#define APIC_VECTOR_MASK 0x000000ffU
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#define APIC_DELMODE_MASK 0x00000700U
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#define APIC_DELMODE_FIXED 0x00000000U
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#define APIC_DELMODE_LOWPRIO 0x00000100U
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#define APIC_DELMODE_SMI 0x00000200U
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#define APIC_DELMODE_RR 0x00000300U
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#define APIC_DELMODE_NMI 0x00000400U
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#define APIC_DELMODE_INIT 0x00000500U
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#define APIC_DELMODE_STARTUP 0x00000600U
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#define APIC_DELMODE_RESV 0x00000700U
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#define APIC_DESTMODE_MASK 0x00000800U
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#define APIC_DESTMODE_PHY 0x00000000U
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#define APIC_DESTMODE_LOG 0x00000800U
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#define APIC_DELSTAT_MASK 0x00001000U
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#define APIC_DELSTAT_IDLE 0x00000000U
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#define APIC_DELSTAT_PEND 0x00001000U
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#define APIC_RESV1_MASK 0x00002000U
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#define APIC_LEVEL_MASK 0x00004000U
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#define APIC_LEVEL_DEASSERT 0x00000000U
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#define APIC_LEVEL_ASSERT 0x00004000U
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#define APIC_TRIGMOD_MASK 0x00008000U
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#define APIC_TRIGMOD_EDGE 0x00000000U
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#define APIC_TRIGMOD_LEVEL 0x00008000U
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#define APIC_RRSTAT_MASK 0x00030000U
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#define APIC_RRSTAT_INVALID 0x00000000U
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#define APIC_RRSTAT_INPROG 0x00010000U
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#define APIC_RRSTAT_VALID 0x00020000U
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#define APIC_RRSTAT_RESV 0x00030000U
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#define APIC_DEST_MASK 0x000c0000U
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#define APIC_DEST_DESTFLD 0x00000000U
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#define APIC_DEST_SELF 0x00040000U
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#define APIC_DEST_ALLISELF 0x00080000U
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#define APIC_DEST_ALLESELF 0x000c0000U
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#define APIC_RESV2_MASK 0xfff00000U
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#define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK)
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/* fields in LVT1/2 */
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#define APIC_LVT_VECTOR 0x000000ffU
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#define APIC_LVT_DM 0x00000700U
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#define APIC_LVT_DM_FIXED 0x00000000U
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#define APIC_LVT_DM_SMI 0x00000200U
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#define APIC_LVT_DM_NMI 0x00000400U
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#define APIC_LVT_DM_INIT 0x00000500U
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#define APIC_LVT_DM_EXTINT 0x00000700U
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#define APIC_LVT_DS 0x00001000U
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#define APIC_LVT_IIPP 0x00002000U
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#define APIC_LVT_IIPP_INTALO 0x00002000U
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#define APIC_LVT_IIPP_INTAHI 0x00000000U
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#define APIC_LVT_RIRR 0x00004000U
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#define APIC_LVT_TM 0x00008000U
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#define APIC_LVT_M 0x00010000U
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/* fields in LVT Timer */
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#define APIC_LVTT_VECTOR 0x000000ffU
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#define APIC_LVTT_DS 0x00001000U
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#define APIC_LVTT_M 0x00010000U
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#define APIC_LVTT_TM 0x00060000U
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#define APIC_LVTT_TM_ONE_SHOT 0x00000000U
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#define APIC_LVTT_TM_PERIODIC 0x00020000U
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#define APIC_LVTT_TM_TSCDLT 0x00040000U
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#define APIC_LVTT_TM_RSRV 0x00060000U
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/* APIC timer current count */
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#define APIC_TIMER_MAX_COUNT 0xffffffffU
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/* fields in TDCR */
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#define APIC_TDCR_2 0x00U
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#define APIC_TDCR_4 0x01U
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#define APIC_TDCR_8 0x02U
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#define APIC_TDCR_16 0x03U
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#define APIC_TDCR_32 0x08U
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#define APIC_TDCR_64 0x09U
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#define APIC_TDCR_128 0x0aU
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#define APIC_TDCR_1 0x0bU
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/* Constants related to AMD Extended APIC Features Register */
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#define APIC_EXTF_ELVT_MASK 0x00ff0000U
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#define APIC_EXTF_ELVT_SHIFT 16
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#define APIC_EXTF_EXTID_CAP 0x00000004U
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#define APIC_EXTF_SEIO_CAP 0x00000002U
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#define APIC_EXTF_IER_CAP 0x00000001U
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/* LVT table indices */
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#define APIC_LVT_TIMER 0U
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#define APIC_LVT_THERMAL 1U
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#define APIC_LVT_PMC 2U
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#define APIC_LVT_LINT0 3U
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#define APIC_LVT_LINT1 4U
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#define APIC_LVT_ERROR 5U
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#define APIC_LVT_CMCI 6U
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#define APIC_LVT_MAX APIC_LVT_CMCI
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/* AMD extended LVT constants, seem to be assigned by fiat */
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#define APIC_ELVT_IBS 0 /* Instruction based sampling */
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#define APIC_ELVT_MCA 1 /* MCE thresholding */
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#define APIC_ELVT_DEI 2 /* Deferred error interrupt */
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#define APIC_ELVT_SBI 3 /* Sideband interface */
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#define APIC_ELVT_MAX APIC_ELVT_SBI
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/******************************************************************************
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* I/O APIC defines
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*/
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/* window register offset */
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#define IOAPIC_REGSEL 0x00U
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#define IOAPIC_WINDOW 0x10U
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/* indexes into IO APIC */
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#define IOAPIC_ID 0x00U
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#define IOAPIC_VER 0x01U
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#define IOAPIC_ARB 0x02U
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#define IOAPIC_REDTBL 0x10U
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#define IOAPIC_REDTBL0 IOAPIC_REDTBL
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#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02U)
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#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04U)
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#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06U)
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#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08U)
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#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0aU)
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#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0cU)
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#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0eU)
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#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10U)
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#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12U)
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#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14U)
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#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16U)
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#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18U)
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#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1aU)
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#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1cU)
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#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1eU)
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#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20U)
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#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22U)
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#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24U)
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#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26U)
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#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28U)
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#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2aU)
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#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2cU)
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#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2eU)
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/* fields in VER, for redirection entry */
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#define IOAPIC_MAX_RTE_MASK 0x00ff0000U
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#define MAX_RTE_SHIFT 16U
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/*
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* fields in the IO APIC's redirection table entries
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*/
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#define IOAPIC_RTE_DEST_SHIFT 56U
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/* broadcast addr: all APICs */
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#define IOAPIC_RTE_DEST_MASK 0xff00000000000000UL
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#define IOAPIC_RTE_RESV 0x00fe0000UL /* reserved */
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#define IOAPIC_RTE_INTMASK 0x00010000UL /* R/W: INTerrupt mask */
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#define IOAPIC_RTE_INTMCLR 0x00000000UL /* clear, allow INTs */
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#define IOAPIC_RTE_INTMSET 0x00010000UL /* set, inhibit INTs */
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#define IOAPIC_RTE_TRGRMOD 0x00008000UL /* R/W: trigger mode */
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#define IOAPIC_RTE_TRGREDG 0x00000000UL /* edge */
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#define IOAPIC_RTE_TRGRLVL 0x00008000UL /* level */
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#define IOAPIC_RTE_REM_IRR 0x00004000UL /* RO: remote IRR */
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#define IOAPIC_RTE_INTPOL 0x00002000UL /*R/W:INT input pin polarity*/
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#define IOAPIC_RTE_INTAHI 0x00000000UL /* active high */
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#define IOAPIC_RTE_INTALO 0x00002000UL /* active low */
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#define IOAPIC_RTE_DELIVS 0x00001000UL /* RO: delivery status */
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#define IOAPIC_RTE_DESTMOD 0x00000800UL /*R/W:destination mode*/
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#define IOAPIC_RTE_DESTPHY 0x00000000UL /* physical */
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#define IOAPIC_RTE_DESTLOG 0x00000800UL /* logical */
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#define IOAPIC_RTE_DELMOD 0x00000700UL /* R/W: delivery mode */
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#define IOAPIC_RTE_DELFIXED 0x00000000UL /* fixed */
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#define IOAPIC_RTE_DELLOPRI 0x00000100UL /* lowest priority */
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#define IOAPIC_RTE_DELSMI 0x00000200UL /*System Management INT*/
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#define IOAPIC_RTE_DELRSV1 0x00000300UL /* reserved */
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#define IOAPIC_RTE_DELNMI 0x00000400UL /* NMI signal */
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#define IOAPIC_RTE_DELINIT 0x00000500UL /* INIT signal */
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#define IOAPIC_RTE_DELRSV2 0x00000600UL /* reserved */
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#define IOAPIC_RTE_DELEXINT 0x00000700UL /* External INTerrupt */
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#define IOAPIC_RTE_INTVEC 0x000000ffUL /*R/W: INT vector field*/
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#endif /* APICREG_H */
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