Binbin Wu 8e310e6ea1 hv: vcpuid: modify vcpuid according to msr ia32_misc_enable ... According to SDM Vol4 2.1, modify vcpuid according to msr ia32_misc_enable: - Clear CPUID.01H: ECX[3] if guest disabled monitor/mwait. - Clear CPUID.80000001H: EDX[20] if guest set XD Bit Disable. - Limit the CPUID leave maximum value to 2 if guest set Limit CPUID MAXVal. Tracked-On: #2834 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2019-05-09 16:35:15 +08:00
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arch/x86	hv: vcpuid: modify vcpuid according to msr ia32_misc_enable	2019-05-09 16:35:15 +08:00
common	hv: release IOMMU irte when releasing ptirq remapping entries	2019-05-06 18:25:37 +08:00
debug	HV: vuart: support MSR and MCR	2019-04-29 15:25:39 +08:00
dm	HV: rename 'type' in struct io_request	2019-05-06 18:25:20 +08:00
hw	hv: move pci.h to include/hw	2019-04-12 10:09:26 +08:00
lib	hv:remove some unnecessary includes	2019-05-07 09:10:13 +08:00
public	hv: add new hypercall to fetch platform configurations	2019-04-15 22:14:13 +08:00