Shuo A Liu 8565750bbe hv: nested: Hide some capability bits from L1 guest ... * Hide 5 level EPT capability, let L1 guest stick to 4 level EPT. * Access/Dirty bits are not support currently, hide corresponding EPT capability bits. * "Mode-based execute control for EPT" is also not support well currently, hide its capability bit from MSR_IA32_VMX_PROCBASED_CTLS2. Tracked-On: #5923 Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2021-06-04 13:53:47 +08:00
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x86	hv: nested: Hide some capability bits from L1 guest	2021-06-04 13:53:47 +08:00