41 lines
1.0 KiB
C
41 lines
1.0 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ZEROPAGE_H
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#define ZEROPAGE_H
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struct zero_page {
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uint8_t pad1[0x1e8]; /* 0x000 */
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uint8_t e820_nentries; /* 0x1e8 */
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uint8_t pad2[0x8]; /* 0x1e9 */
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struct {
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uint8_t setup_sects; /* 0x1f1 */
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uint8_t hdr_pad1[0x1e]; /* 0x1f2 */
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uint8_t loader_type; /* 0x210 */
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uint8_t load_flags; /* 0x211 */
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uint8_t hdr_pad2[0x6]; /* 0x212 */
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uint32_t ramdisk_addr; /* 0x218 */
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uint32_t ramdisk_size; /* 0x21c */
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uint8_t hdr_pad3[0x8]; /* 0x220 */
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uint32_t bootargs_addr; /* 0x228 */
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uint8_t hdr_pad4[0x8]; /* 0x22c */
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uint8_t relocatable_kernel; /* 0x234 */
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uint8_t hdr_pad5[0x13]; /* 0x235 */
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uint32_t payload_offset;/* 0x248 */
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uint32_t payload_length;/* 0x24c */
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uint8_t hdr_pad6[0x8]; /* 0x250 */
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uint64_t pref_addr; /* 0x258 */
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uint8_t hdr_pad7[8]; /* 0x260 */
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} __packed hdr;
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uint8_t pad3[0x68]; /* 0x268 */
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struct e820_entry entries[0x80]; /* 0x2d0 */
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uint8_t pad4[0x330]; /* 0xcd0 */
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} __packed;
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#endif
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