184 lines
5.4 KiB
C
184 lines
5.4 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef PCI_H_
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#define PCI_H_
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/*
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* PCIM_xxx: mask to locate subfield in register
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* PCIR_xxx: config register offset
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* PCIC_xxx: device class
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* PCIS_xxx: device subclass
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* PCIP_xxx: device programming interface
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* PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
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* PCID_xxx: device ID
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* PCIY_xxx: capability identification number
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* PCIZ_xxx: extended capability identification number
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*/
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/* some PCI bus constants */
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#define PCI_BUSMAX 0xFFU
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#define PCI_SLOTMAX 0x1FU
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#define PCI_FUNCMAX 0x7U
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#define PCI_BAR_COUNT 0x6U
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#define PCI_REGMAX 0xFFU
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/* I/O ports */
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#define PCI_CONFIG_ADDR 0xCF8U
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#define PCI_CONFIG_DATA 0xCFCU
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#define PCI_CFG_ENABLE 0x80000000U
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/* PCI config header registers for all devices */
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#define PCIR_VENDOR 0x00U
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#define PCIR_DEVICE 0x02U
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#define PCIR_COMMAND 0x04U
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#define PCIM_CMD_INTxDIS 0x400U
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#define PCIR_STATUS 0x06U
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#define PCIM_STATUS_CAPPRESENT 0x0010U
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#define PCIR_REVID 0x08U
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#define PCIR_SUBCLASS 0x0AU
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#define PCIR_CLASS 0x0BU
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#define PCIR_HDRTYPE 0x0EU
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#define PCIM_HDRTYPE 0x7FU
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#define PCIM_HDRTYPE_NORMAL 0x00U
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#define PCIM_HDRTYPE_BRIDGE 0x01U
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#define PCIM_MFDEV 0x80U
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#define PCIR_BARS 0x10U
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#define PCIM_BAR_SPACE 0x01U
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#define PCIM_BAR_IO_SPACE 0x01U
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#define PCIM_BAR_MEM_TYPE 0x06U
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#define PCIM_BAR_MEM_32 0x00U
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#define PCIM_BAR_MEM_1MB 0x02U
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#define PCIM_BAR_MEM_64 0x04U
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#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
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#define PCIR_CAP_PTR 0x34U
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/* config registers for header type 1 (PCI-to-PCI bridge) devices */
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#define PCIR_PRIBUS_1 0x18U
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#define PCIR_SECBUS_1 0x19U
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#define PCIR_SUBBUS_1 0x1AU
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/* Capability Register Offsets */
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#define PCICAP_ID 0x0U
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#define PCICAP_NEXTPTR 0x1U
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/* Capability Identification Numbers */
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#define PCIY_MSI 0x05U
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#define PCIY_MSIX 0x11U
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/* PCI Message Signalled Interrupts (MSI) */
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#define PCIR_MSI_CTRL 0x02U
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#define PCIM_MSICTRL_64BIT 0x80U
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#define PCIM_MSICTRL_MSI_ENABLE 0x01U
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#define PCIR_MSI_ADDR 0x4U
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#define PCIR_MSI_ADDR_HIGH 0x8U
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#define PCIR_MSI_DATA 0x8U
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#define PCIR_MSI_DATA_64BIT 0xCU
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#define PCIR_MSI_MASK 0x10U
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#define PCIM_MSICTRL_MMC_MASK 0x000EU
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#define PCIM_MSICTRL_MME_MASK 0x0070U
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/* PCI device class */
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#define PCIC_BRIDGE 0x06U
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#define PCIS_BRIDGE_HOST 0x00U
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/* MSI-X definitions */
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#define PCIR_MSIX_CTRL 0x2U
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#define PCIR_MSIX_TABLE 0x4U
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#define PCIR_MSIX_PBA 0x8U
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#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000U
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#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000U
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#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FFU
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#define PCIM_MSIX_BIR_MASK 0x7U
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#define PCIM_MSIX_VCTRL_MASK 0x1U
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#define MSIX_CAPLEN 12U
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#define MSIX_TABLE_ENTRY_SIZE 16U
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union pci_bdf {
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uint16_t value;
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struct {
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uint8_t f : 3; /* BITs 0-2 */
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uint8_t d : 5; /* BITs 3-7 */
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uint8_t b; /* BITs 8-15 */
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} bits;
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};
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enum pci_bar_type {
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PCIBAR_NONE = 0,
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PCIBAR_MEM32,
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PCIBAR_MEM64,
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};
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typedef void (*pci_enumeration_cb)(uint16_t pbdf, void *data);
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static inline uint32_t pci_bar_offset(uint32_t idx)
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{
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return PCIR_BARS + (idx << 2U);
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}
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static inline bool pci_bar_access(uint32_t offset)
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{
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bool ret;
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if ((offset >= pci_bar_offset(0U))
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&& (offset < pci_bar_offset(PCI_BAR_COUNT))) {
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ret = true;
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} else {
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ret = false;
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}
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return ret;
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}
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static inline uint8_t pci_bus(uint16_t bdf)
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{
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return (uint8_t)((bdf >> 8U) & 0xFFU);
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}
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static inline uint8_t pci_slot(uint16_t bdf)
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{
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return (uint8_t)((bdf >> 3U) & 0x1FU);
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}
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static inline uint8_t pci_func(uint16_t bdf)
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{
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return (uint8_t)(bdf & 0x7U);
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}
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uint32_t pci_pdev_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes);
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void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val);
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void enable_disable_pci_intx(union pci_bdf bdf, bool enable);
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void pci_scan_bus(pci_enumeration_cb cb, void *cb_data);
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#endif /* PCI_H_ */
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