489 lines
13 KiB
C
489 lines
13 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hypervisor.h>
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#define EXCEPTION_ERROR_CODE_VALID 8
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#define INTERRPUT_QUEUE_BUFF_SIZE 255
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#define ACRN_DBG_INTR 6
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static const uint16_t exception_type[] = {
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[0] = VMX_INT_TYPE_HW_EXP,
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[1] = VMX_INT_TYPE_HW_EXP,
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[2] = VMX_INT_TYPE_HW_EXP,
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[3] = VMX_INT_TYPE_HW_EXP,
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[4] = VMX_INT_TYPE_HW_EXP,
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[5] = VMX_INT_TYPE_HW_EXP,
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[6] = VMX_INT_TYPE_HW_EXP,
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[7] = VMX_INT_TYPE_HW_EXP,
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[8] = VMX_INT_TYPE_HW_EXP | EXCEPTION_ERROR_CODE_VALID,
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[9] = VMX_INT_TYPE_HW_EXP,
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[10] = VMX_INT_TYPE_HW_EXP | EXCEPTION_ERROR_CODE_VALID,
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[11] = VMX_INT_TYPE_HW_EXP | EXCEPTION_ERROR_CODE_VALID,
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[12] = VMX_INT_TYPE_HW_EXP | EXCEPTION_ERROR_CODE_VALID,
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[13] = VMX_INT_TYPE_HW_EXP | EXCEPTION_ERROR_CODE_VALID,
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[14] = VMX_INT_TYPE_HW_EXP | EXCEPTION_ERROR_CODE_VALID,
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[15] = VMX_INT_TYPE_HW_EXP,
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[16] = VMX_INT_TYPE_HW_EXP,
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[17] = VMX_INT_TYPE_HW_EXP | EXCEPTION_ERROR_CODE_VALID,
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[18] = VMX_INT_TYPE_HW_EXP,
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[19] = VMX_INT_TYPE_HW_EXP,
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[20] = VMX_INT_TYPE_HW_EXP,
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[21] = VMX_INT_TYPE_HW_EXP,
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[22] = VMX_INT_TYPE_HW_EXP,
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[23] = VMX_INT_TYPE_HW_EXP,
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[24] = VMX_INT_TYPE_HW_EXP,
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[25] = VMX_INT_TYPE_HW_EXP,
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[26] = VMX_INT_TYPE_HW_EXP,
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[27] = VMX_INT_TYPE_HW_EXP,
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[28] = VMX_INT_TYPE_HW_EXP,
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[29] = VMX_INT_TYPE_HW_EXP,
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[30] = VMX_INT_TYPE_HW_EXP,
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[31] = VMX_INT_TYPE_HW_EXP
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};
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static int is_guest_irq_enabled(struct vcpu *vcpu)
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{
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struct run_context *cur_context =
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&vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context];
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uint32_t guest_rflags, guest_state;
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int status = false;
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/* Read the RFLAGS of the guest */
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guest_rflags = cur_context->rflags;
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/* Check the RFLAGS[IF] bit first */
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if (guest_rflags & HV_ARCH_VCPU_RFLAGS_IF) {
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/* Interrupts are allowed */
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/* Check for temporarily disabled interrupts */
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guest_state = exec_vmread(VMX_GUEST_INTERRUPTIBILITY_INFO);
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if ((guest_state & (HV_ARCH_VCPU_BLOCKED_BY_STI |
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HV_ARCH_VCPU_BLOCKED_BY_MOVSS)) == 0) {
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status = true;
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}
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}
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return status;
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}
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static bool vcpu_pending_request(struct vcpu *vcpu)
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{
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struct vlapic *vlapic;
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int vector = 0;
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int ret = 0;
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/* Query vLapic to get vector to inject */
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vlapic = vcpu->arch_vcpu.vlapic;
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ret = vlapic_pending_intr(vlapic, &vector);
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/* we need to check and raise request if we have pending event
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* in LAPIC IRR
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*/
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if (ret != 0) {
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/* we have pending IRR */
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vcpu_make_request(vcpu, ACRN_REQUEST_EVENT);
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}
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return vcpu->arch_vcpu.pending_intr != 0;
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}
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int vcpu_make_request(struct vcpu *vcpu, int eventid)
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{
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bitmap_set(eventid, &vcpu->arch_vcpu.pending_intr);
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/*
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* if current hostcpu is not the target vcpu's hostcpu, we need
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* to invoke IPI to wake up target vcpu
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*
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* TODO: Here we just compare with cpuid, since cpuid currently is
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* global under pCPU / vCPU 1:1 mapping. If later we enabled vcpu
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* scheduling, we need change here to determine it target vcpu is
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* VMX non-root or root mode
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*/
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if ((int)get_cpu_id() != vcpu->pcpu_id)
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send_single_ipi(vcpu->pcpu_id, VECTOR_NOTIFY_VCPU);
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return 0;
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}
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static int vcpu_do_pending_event(struct vcpu *vcpu)
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{
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struct vlapic *vlapic = vcpu->arch_vcpu.vlapic;
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int vector = 0;
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int ret = 0;
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if (is_vapic_intr_delivery_supported()) {
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apicv_inject_pir(vlapic);
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return 0;
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}
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/* Query vLapic to get vector to inject */
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ret = vlapic_pending_intr(vlapic, &vector);
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/*
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* From the Intel SDM, Volume 3, 6.3.2 Section "Maskable
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* Hardware Interrupts":
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* - maskable interrupt vectors [16,255] can be delivered
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* through the local APIC.
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*/
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if (ret == 0)
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return -1;
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if (!(vector >= 16 && vector <= 255)) {
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dev_dbg(ACRN_DBG_INTR, "invalid vector %d from local APIC",
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vector);
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return -1;
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}
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exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD, VMX_INT_INFO_VALID |
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(vector & 0xFF));
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vlapic_intr_accepted(vlapic, vector);
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return 0;
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}
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static int vcpu_do_pending_extint(struct vcpu *vcpu)
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{
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struct vm *vm;
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struct vcpu *primary;
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int vector;
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vm = vcpu->vm;
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/* check if there is valid interrupt from vPIC, if yes just inject it */
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/* PIC only connect with primary CPU */
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primary = get_primary_vcpu(vm);
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if (vm->vpic && vcpu == primary) {
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vpic_pending_intr(vcpu->vm, &vector);
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if (vector > 0) {
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dev_dbg(ACRN_DBG_INTR, "VPIC: to inject PIC vector %d\n",
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vector & 0xFF);
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exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD,
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VMX_INT_INFO_VALID |
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(vector & 0xFF));
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vpic_intr_accepted(vcpu->vm, vector);
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}
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}
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return 0;
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}
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static int vcpu_do_pending_gp(__unused struct vcpu *vcpu)
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{
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/* SDM Vol. 3A 6-37: if the fault condition was detected while loading
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* a segment descriptor, the error code contains a segment selecor to or
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* IDT vector number for the descriptor; otherwise the error code is 0.
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* Since currently there is no such case to inject #GP due to loading a
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* segment decriptor, set the error code to 0.
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*/
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exec_vmwrite(VMX_ENTRY_EXCEPTION_ERROR_CODE, 0);
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/* GP vector = 13 */
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exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD,
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VMX_INT_INFO_VALID |
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((VMX_INT_TYPE_HW_EXP | EXCEPTION_ERROR_CODE_VALID) << 8) |
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IDT_GP);
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return 0;
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}
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/* please keep this for interrupt debug:
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* 1. Timer alive or not
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* 2. native LAPIC interrupt pending/EOI status
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* 3. CPU stuck or not
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*/
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void dump_lapic(void)
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{
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dev_dbg(ACRN_DBG_INTR,
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"LAPIC: TIME %08x, init=0x%x cur=0x%x ISR=0x%x IRR=0x%x",
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mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_LVT_TIMER_REGISTER)),
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mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_INITIAL_COUNT_REGISTER)),
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mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_CURRENT_COUNT_REGISTER)),
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mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_IN_SERVICE_REGISTER_7)),
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mmio_read_long(HPA2HVA(LAPIC_BASE + LAPIC_INT_REQUEST_REGISTER_7)));
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}
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int vcpu_inject_extint(struct vcpu *vcpu)
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{
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return vcpu_make_request(vcpu, ACRN_REQUEST_EXTINT);
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}
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int vcpu_inject_nmi(struct vcpu *vcpu)
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{
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return vcpu_make_request(vcpu, ACRN_REQUEST_NMI);
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}
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int vcpu_inject_gp(struct vcpu *vcpu)
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{
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return vcpu_make_request(vcpu, ACRN_REQUEST_GP);
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}
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int interrupt_window_vmexit_handler(struct vcpu *vcpu)
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{
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int value32;
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TRACE_2L(TRC_VMEXIT_INTERRUPT_WINDOW, 0, 0);
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if (!vcpu)
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return -1;
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if (vcpu_pending_request(vcpu)) {
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/* Do nothing
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* acrn_do_intr_process will continue for this vcpu
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*/
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} else {
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/* No interrupts to inject.
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* Disable the interrupt window exiting
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*/
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vcpu->arch_vcpu.irq_window_enabled = 0;
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value32 = exec_vmread(VMX_PROC_VM_EXEC_CONTROLS);
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value32 &= ~(VMX_PROCBASED_CTLS_IRQ_WIN);
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exec_vmwrite(VMX_PROC_VM_EXEC_CONTROLS, value32);
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}
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VCPU_RETAIN_RIP(vcpu);
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return 0;
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}
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int external_interrupt_vmexit_handler(struct vcpu *vcpu)
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{
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uint32_t intr_info;
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struct intr_excp_ctx ctx;
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intr_info = exec_vmread(VMX_EXIT_INT_INFO);
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if ((!(intr_info & VMX_INT_INFO_VALID)) ||
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(((intr_info & VMX_INT_TYPE_MASK) >> 8)
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!= VMX_INT_TYPE_EXT_INT)) {
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pr_err("Invalid VM exit interrupt info:%x", intr_info);
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VCPU_RETAIN_RIP(vcpu);
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return -EINVAL;
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}
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ctx.vector = intr_info & 0xFF;
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dispatch_interrupt(&ctx);
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VCPU_RETAIN_RIP(vcpu);
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TRACE_2L(TRC_VMEXIT_EXTERNAL_INTERRUPT, ctx.vector, 0);
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return 0;
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}
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int acrn_do_intr_process(struct vcpu *vcpu)
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{
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int ret = 0;
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int vector;
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int tmp;
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bool intr_pending = false;
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uint64_t *pending_intr_bits = &vcpu->arch_vcpu.pending_intr;
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if (bitmap_test_and_clear(ACRN_REQUEST_TLB_FLUSH, pending_intr_bits))
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invept(vcpu);
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if (bitmap_test_and_clear(ACRN_REQUEST_TMR_UPDATE, pending_intr_bits))
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vioapic_update_tmr(vcpu);
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/* handling cancelled event injection when vcpu is switched out */
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if (vcpu->arch_vcpu.inject_event_pending) {
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exec_vmwrite(VMX_ENTRY_EXCEPTION_ERROR_CODE,
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vcpu->arch_vcpu.inject_info.error_code);
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exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD,
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vcpu->arch_vcpu.inject_info.intr_info);
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vcpu->arch_vcpu.inject_event_pending = false;
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goto INTR_WIN;
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}
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/* handling pending vector injection:
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* there are many reason inject failed, we need re-inject again
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*/
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if (vcpu->arch_vcpu.idt_vectoring_info & VMX_INT_INFO_VALID) {
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exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD,
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vcpu->arch_vcpu.idt_vectoring_info);
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goto INTR_WIN;
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}
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/* handling exception request */
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vector = vcpu->arch_vcpu.exception_info.exception;
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/* If there is a valid exception, inject exception to guest */
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if (vector >= 0) {
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if (exception_type[vector] &
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EXCEPTION_ERROR_CODE_VALID) {
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exec_vmwrite(VMX_ENTRY_EXCEPTION_ERROR_CODE,
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vcpu->arch_vcpu.exception_info.error);
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}
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exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD,
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VMX_INT_INFO_VALID |
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(exception_type[vector] << 8) | (vector & 0xFF));
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vcpu->arch_vcpu.exception_info.exception = -1;
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goto INTR_WIN;
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}
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/* Do pending interrupts process */
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/* TODO: checkin NMI intr windows before inject */
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if (bitmap_test_and_clear(ACRN_REQUEST_NMI, pending_intr_bits)) {
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/* Inject NMI vector = 2 */
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exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD,
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VMX_INT_INFO_VALID | (VMX_INT_TYPE_NMI << 8) | IDT_NMI);
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/* Intel SDM 10.8.1
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* NMI, SMI, INIT, ExtINT, or SIPI directly deliver to CPU
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* do not need EOI to LAPIC
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* However, ExtINT need EOI to PIC
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*/
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goto INTR_WIN;
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}
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/* Guest interruptable or not */
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if (is_guest_irq_enabled(vcpu)) {
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/* Inject external interrupt first */
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if (bitmap_test_and_clear(ACRN_REQUEST_EXTINT,
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pending_intr_bits)) {
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/* has pending external interrupts */
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ret = vcpu_do_pending_extint(vcpu);
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goto INTR_WIN;
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}
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/* Inject vLAPIC vectors */
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if (bitmap_test_and_clear(ACRN_REQUEST_EVENT,
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pending_intr_bits)) {
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/* has pending vLAPIC interrupts */
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ret = vcpu_do_pending_event(vcpu);
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goto INTR_WIN;
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}
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}
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/* Inject GP event */
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if (bitmap_test_and_clear(ACRN_REQUEST_GP, pending_intr_bits)) {
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/* has pending GP interrupts */
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ret = vcpu_do_pending_gp(vcpu);
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goto INTR_WIN;
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}
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INTR_WIN:
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/* check if we have new interrupt pending for next VMExit */
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intr_pending = vcpu_pending_request(vcpu);
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/* Enable interrupt window exiting if pending */
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if (intr_pending && vcpu->arch_vcpu.irq_window_enabled == 0) {
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vcpu->arch_vcpu.irq_window_enabled = 1;
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tmp = exec_vmread(VMX_PROC_VM_EXEC_CONTROLS);
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tmp |= (VMX_PROCBASED_CTLS_IRQ_WIN);
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exec_vmwrite(VMX_PROC_VM_EXEC_CONTROLS, tmp);
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}
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return ret;
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}
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void cancel_event_injection(struct vcpu *vcpu)
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{
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uint32_t intinfo;
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intinfo = exec_vmread(VMX_ENTRY_INT_INFO_FIELD);
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/*
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* If event is injected, we clear VMX_ENTRY_INT_INFO_FIELD,
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* save injection info, and mark inject event pending.
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* The event will be re-injected in next acrn_do_intr_process
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* call.
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*/
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if (intinfo & VMX_INT_INFO_VALID) {
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vcpu->arch_vcpu.inject_event_pending = true;
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if (intinfo & (EXCEPTION_ERROR_CODE_VALID << 8))
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vcpu->arch_vcpu.inject_info.error_code =
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exec_vmread(VMX_ENTRY_EXCEPTION_ERROR_CODE);
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vcpu->arch_vcpu.inject_info.intr_info = intinfo;
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exec_vmwrite(VMX_ENTRY_INT_INFO_FIELD, 0);
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}
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}
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int exception_vmexit_handler(struct vcpu *vcpu)
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{
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uint32_t intinfo, int_err_code = 0;
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int32_t exception_vector = -1;
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uint32_t cpl;
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int status = 0;
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if (vcpu == NULL) {
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TRACE_4I(TRC_VMEXIT_EXCEPTION_OR_NMI, 0, 0, 0, 0);
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status = -EINVAL;
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}
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if (status != 0)
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return status;
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pr_dbg(" Handling guest exception");
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/* Obtain VM-Exit information field pg 2912 */
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intinfo = exec_vmread(VMX_EXIT_INT_INFO);
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if (intinfo & VMX_INT_INFO_VALID) {
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exception_vector = intinfo & 0xFF;
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/* Check if exception caused by the guest is a HW exception.
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* If the exit occurred due to a HW exception obtain the
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* error code to be conveyed to get via the stack
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*/
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if (intinfo & VMX_INT_INFO_ERR_CODE_VALID) {
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int_err_code = exec_vmread(VMX_EXIT_INT_ERROR_CODE);
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/* get current privilege level and fault address */
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cpl = exec_vmread(VMX_GUEST_CS_ATTR);
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cpl = (cpl >> 5) & 3;
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if (cpl < 3)
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int_err_code &= ~4;
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else
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int_err_code |= 4;
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}
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}
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/* Handle all other exceptions */
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VCPU_RETAIN_RIP(vcpu);
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vcpu->arch_vcpu.exception_info.exception = exception_vector;
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vcpu->arch_vcpu.exception_info.error = int_err_code;
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if (exception_vector == IDT_MC) {
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/* just print error message for #MC, it then will be injected
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* back to guest */
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pr_fatal("Exception #MC got from guest!");
|
|
}
|
|
|
|
TRACE_4I(TRC_VMEXIT_EXCEPTION_OR_NMI,
|
|
exception_vector, int_err_code, 2, 0);
|
|
|
|
return status;
|
|
}
|