174 lines
5.8 KiB
C
174 lines
5.8 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef INTR_LAPIC_H
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#define INTR_LAPIC_H
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#define DEBUG_LAPIC 0
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enum intr_lapic_icr_delivery_mode {
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INTR_LAPIC_ICR_FIXED = 0x0,
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INTR_LAPIC_ICR_LP = 0x1,
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INTR_LAPIC_ICR_SMI = 0x2,
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INTR_LAPIC_ICR_NMI = 0x4,
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INTR_LAPIC_ICR_INIT = 0x5,
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INTR_LAPIC_ICR_STARTUP = 0x6,
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};
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enum intr_lapic_icr_dest_mode {
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INTR_LAPIC_ICR_PHYSICAL = 0x0,
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INTR_LAPIC_ICR_LOGICAL = 0x1
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};
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enum intr_lapic_icr_level {
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INTR_LAPIC_ICR_DEASSERT = 0x0,
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INTR_LAPIC_ICR_ASSERT = 0x1,
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};
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enum intr_lapic_icr_trigger {
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INTR_LAPIC_ICR_EDGE = 0x0,
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INTR_LAPIC_ICR_LEVEL = 0x1,
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};
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enum intr_lapic_icr_shorthand {
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INTR_LAPIC_ICR_USE_DEST_ARRAY = 0x0,
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INTR_LAPIC_ICR_SELF = 0x1,
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INTR_LAPIC_ICR_ALL_INC_SELF = 0x2,
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INTR_LAPIC_ICR_ALL_EX_SELF = 0x3,
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};
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/* Default LAPIC base */
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#define LAPIC_BASE 0xFEE00000U
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/* LAPIC register offset for memory mapped IO access */
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#define LAPIC_ID_REGISTER 0x00000020U
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#define LAPIC_VERSION_REGISTER 0x00000030U
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#define LAPIC_TASK_PRIORITY_REGISTER 0x00000080U
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#define LAPIC_ARBITRATION_PRIORITY_REGISTER 0x00000090U
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#define LAPIC_PROCESSOR_PRIORITY_REGISTER 0x000000A0U
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#define LAPIC_EOI_REGISTER 0x000000B0U
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#define LAPIC_REMOTE_READ_REGISTER 0x000000C0U
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#define LAPIC_LOGICAL_DESTINATION_REGISTER 0x000000D0U
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#define LAPIC_DESTINATION_FORMAT_REGISTER 0x000000E0U
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#define LAPIC_SPURIOUS_VECTOR_REGISTER 0x000000F0U
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#define LAPIC_IN_SERVICE_REGISTER_0 0x00000100U
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#define LAPIC_IN_SERVICE_REGISTER_1 0x00000110U
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#define LAPIC_IN_SERVICE_REGISTER_2 0x00000120U
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#define LAPIC_IN_SERVICE_REGISTER_3 0x00000130U
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#define LAPIC_IN_SERVICE_REGISTER_4 0x00000140U
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#define LAPIC_IN_SERVICE_REGISTER_5 0x00000150U
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#define LAPIC_IN_SERVICE_REGISTER_6 0x00000160U
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#define LAPIC_IN_SERVICE_REGISTER_7 0x00000170U
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#define LAPIC_TRIGGER_MODE_REGISTER_0 0x00000180U
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#define LAPIC_TRIGGER_MODE_REGISTER_1 0x00000190U
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#define LAPIC_TRIGGER_MODE_REGISTER_2 0x000001A0U
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#define LAPIC_TRIGGER_MODE_REGISTER_3 0x000001B0U
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#define LAPIC_TRIGGER_MODE_REGISTER_4 0x000001C0U
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#define LAPIC_TRIGGER_MODE_REGISTER_5 0x000001D0U
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#define LAPIC_TRIGGER_MODE_REGISTER_6 0x000001E0U
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#define LAPIC_TRIGGER_MODE_REGISTER_7 0x000001F0U
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#define LAPIC_INT_REQUEST_REGISTER_0 0x00000200U
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#define LAPIC_INT_REQUEST_REGISTER_1 0x00000210U
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#define LAPIC_INT_REQUEST_REGISTER_2 0x00000220U
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#define LAPIC_INT_REQUEST_REGISTER_3 0x00000230U
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#define LAPIC_INT_REQUEST_REGISTER_4 0x00000240U
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#define LAPIC_INT_REQUEST_REGISTER_5 0x00000250U
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#define LAPIC_INT_REQUEST_REGISTER_6 0x00000260U
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#define LAPIC_INT_REQUEST_REGISTER_7 0x00000270U
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#define LAPIC_ERROR_STATUS_REGISTER 0x00000280U
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#define LAPIC_LVT_CMCI_REGISTER 0x000002F0U
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#define LAPIC_INT_COMMAND_REGISTER_0 0x00000300U
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#define LAPIC_INT_COMMAND_REGISTER_1 0x00000310U
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#define LAPIC_LVT_TIMER_REGISTER 0x00000320U
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#define LAPIC_LVT_THERMAL_SENSOR_REGISTER 0x00000330U
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#define LAPIC_LVT_PMC_REGISTER 0x00000340U
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#define LAPIC_LVT_LINT0_REGISTER 0x00000350U
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#define LAPIC_LVT_LINT1_REGISTER 0x00000360U
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#define LAPIC_LVT_ERROR_REGISTER 0x00000370U
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#define LAPIC_INITIAL_COUNT_REGISTER 0x00000380U
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#define LAPIC_CURRENT_COUNT_REGISTER 0x00000390U
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#define LAPIC_DIVIDE_CONFIGURATION_REGISTER 0x000003E0U
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/* LAPIC CPUID bit and bitmask definitions */
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#define CPUID_OUT_RDX_APIC_PRESENT ((uint64_t) 1UL << 9)
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#define CPUID_OUT_RCX_X2APIC_PRESENT ((uint64_t) 1UL << 21)
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/* LAPIC MSR bit and bitmask definitions */
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#define MSR_01B_XAPIC_GLOBAL_ENABLE ((uint64_t) 1UL << 11)
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/* LAPIC register bit and bitmask definitions */
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#define LAPIC_SVR_VECTOR 0x000000FFU
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#define LAPIC_SVR_APIC_ENABLE_MASK 0x00000100U
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#define LAPIC_LVT_MASK 0x00010000U
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#define LAPIC_DELIVERY_MODE_EXTINT_MASK 0x00000700U
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/* LAPIC Timer bit and bitmask definitions */
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#define LAPIC_TMR_ONESHOT ((uint32_t) 0x0U << 17)
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#define LAPIC_TMR_PERIODIC ((uint32_t) 0x1U << 17)
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#define LAPIC_TMR_TSC_DEADLINE ((uint32_t) 0x2U << 17)
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enum intr_cpu_startup_shorthand {
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INTR_CPU_STARTUP_USE_DEST,
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INTR_CPU_STARTUP_ALL_EX_SELF,
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INTR_CPU_STARTUP_UNKNOWN,
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};
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union lapic_id {
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uint32_t value;
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struct {
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uint8_t xapic_id;
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uint8_t rsvd[3];
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} xapic;
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union {
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uint32_t value;
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struct {
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uint8_t xapic_id;
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uint8_t xapic_edid;
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uint8_t rsvd[2];
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} ioxapic_view;
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struct {
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uint32_t x2apic_id:4;
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uint32_t x2apic_cluster:28;
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} ldr_view;
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} x2apic;
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};
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struct lapic_regs {
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uint32_t id;
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uint32_t tpr;
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uint32_t apr;
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uint32_t ppr;
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uint32_t ldr;
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uint32_t dfr;
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uint32_t tmr[8];
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uint32_t svr;
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uint32_t lvtt;
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uint32_t lvt0;
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uint32_t lvt1;
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uint32_t lvterr;
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uint32_t ticr;
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uint32_t tccr;
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uint32_t tdcr;
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};
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void write_lapic_reg32(uint32_t offset, uint32_t value);
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void save_lapic(struct lapic_regs *regs);
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int early_init_lapic(void);
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int init_lapic(uint16_t cpu_id);
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void send_lapic_eoi(void);
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uint32_t get_cur_lapic_id(void);
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int send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
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uint32_t cpu_startup_dest,
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uint64_t cpu_startup_start_address);
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/* API to send an IPI to a single guest */
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void send_single_ipi(uint16_t pcpu_id, uint32_t vector);
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void suspend_lapic(void);
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void resume_lapic(void);
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#endif /* INTR_LAPIC_H */
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