340 lines
8.9 KiB
C
340 lines
8.9 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IO_H
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#define IO_H
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/* Definition of a IO port range */
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struct vm_io_range {
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uint16_t base; /* IO port base */
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uint16_t len; /* IO port range */
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int flags; /* IO port attributes */
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};
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/* Write 1 byte to specified I/O port */
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static inline void io_write_byte(uint8_t value, uint16_t port)
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{
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asm volatile ("outb %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 1 byte from specified I/O port */
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static inline uint8_t io_read_byte(uint16_t port)
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{
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uint8_t value;
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asm volatile ("inb %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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/* Write 2 bytes to specified I/O port */
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static inline void io_write_word(uint16_t value, uint16_t port)
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{
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asm volatile ("outw %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 2 bytes from specified I/O port */
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static inline uint16_t io_read_word(uint16_t port)
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{
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uint16_t value;
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asm volatile ("inw %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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/* Write 4 bytes to specified I/O port */
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static inline void io_write_long(uint32_t value, uint16_t port)
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{
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asm volatile ("outl %0,%1"::"a" (value), "dN"(port));
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}
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/* Read 4 bytes from specified I/O port */
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static inline uint32_t io_read_long(uint16_t port)
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{
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uint32_t value;
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asm volatile ("inl %1,%0":"=a" (value):"dN"(port));
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return value;
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}
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static inline void io_write(uint32_t v, uint16_t addr, size_t sz)
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{
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if (sz == 1)
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io_write_byte(v, addr);
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else if (sz == 2)
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io_write_word(v, addr);
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else
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io_write_long(v, addr);
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}
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static inline uint32_t io_read(uint16_t addr, size_t sz)
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{
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if (sz == 1)
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return io_read_byte(addr);
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if (sz == 2)
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return io_read_word(addr);
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return io_read_long(addr);
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}
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struct vm_io_handler;
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struct vm;
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struct vcpu;
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typedef
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uint32_t (*io_read_fn_t)(struct vm_io_handler *, struct vm *,
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uint16_t, size_t);
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typedef
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void (*io_write_fn_t)(struct vm_io_handler *, struct vm *,
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uint16_t, size_t, uint32_t);
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/* Describes a single IO handler description entry. */
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struct vm_io_handler_desc {
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/** The base address of the IO range for this description. */
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uint16_t addr;
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/** The number of bytes covered by this description. */
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size_t len;
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/** A pointer to the "read" function.
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*
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* The read function is called from the hypervisor whenever
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* a read access to a range described in "ranges" occur.
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* The arguments to the callback are:
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*
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* - The address of the port to read from.
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* - The width of the read operation (1,2 or 4).
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*
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* The implementation must return the ports content as
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* byte, word or doubleword (depending on the width).
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*
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* If the pointer is null, a read of 1's is assumed.
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*/
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io_read_fn_t io_read;
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/** A pointer to the "write" function.
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*
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* The write function is called from the hypervisor code
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* whenever a write access to a range described in "ranges"
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* occur. The arguments to the callback are:
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*
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* - The address of the port to write to.
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* - The width of the write operation (1,2 or 4).
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* - The value to write as byte, word or doubleword
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* (depending on the width)
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*
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* The implementation must write the value to the port.
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*
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* If the pointer is null, the write access is ignored.
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*/
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io_write_fn_t io_write;
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};
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struct vm_io_handler {
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struct vm_io_handler *next;
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struct vm_io_handler_desc desc;
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};
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#define IO_ATTR_R 0
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#define IO_ATTR_RW 1
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#define IO_ATTR_NO_ACCESS 2
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/* External Interfaces */
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int io_instr_vmexit_handler(struct vcpu *vcpu);
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void setup_io_bitmap(struct vm *vm);
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void free_io_emulation_resource(struct vm *vm);
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void allow_guest_io_access(struct vm *vm, uint32_t address, uint32_t nbytes);
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void register_io_emulation_handler(struct vm *vm, struct vm_io_range *range,
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io_read_fn_t io_read_fn_ptr,
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io_write_fn_t io_write_fn_ptr);
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int dm_emulate_pio_post(struct vcpu *vcpu);
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/** Writes a 32 bit value to a memory mapped IO device.
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*
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* @param value The 32 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void mmio_write_long(uint32_t value, void *addr)
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{
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*((volatile int32_t *)addr) = value;
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}
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/** Writes a 16 bit value to a memory mapped IO device.
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*
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* @param value The 16 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void mmio_write_word(uint32_t value, void *addr)
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{
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*((volatile uint16_t *)addr) = value;
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}
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/** Writes an 8 bit value to a memory mapped IO device.
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*
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* @param value The 8 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void mmio_write_byte(uint32_t value, void *addr)
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{
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*((volatile uint8_t *)addr) = value;
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}
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/** Reads a 32 bit value from a memory mapped IO device.
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*
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* @param addr The memory address to read from.
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*
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* @return The 32 bit value read from the given address.
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*/
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static inline uint32_t mmio_read_long(void *addr)
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{
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return *((volatile uint32_t *)addr);
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}
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/** Reads a 16 bit value from a memory mapped IO device.
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*
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* @param addr The memory address to read from.
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*
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* @return The 16 bit value read from the given address.
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*/
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static inline uint16_t mmio_read_word(void *addr)
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{
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return *((volatile uint16_t *)addr);
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}
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/** Reads an 8 bit value from a memory mapped IO device.
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*
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* @param addr The memory address to read from.
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*
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* @return The 8 bit value read from the given address.
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*/
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static inline uint8_t mmio_read_byte(void *addr)
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{
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return *((volatile uint8_t *)addr);
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}
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/** Writes a 32 bit value to a memory mapped IO device (ROM code version).
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*
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* @param value The 32 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void __mmio_write_long(uint32_t value, void *addr)
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{
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*((volatile uint32_t *)addr) = value;
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}
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/** Writes a 16 bit value to a memory mapped IO device (ROM code version).
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*
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* @param value The 16 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void __mmio_write_word(uint32_t value, void *addr)
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{
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*((volatile uint16_t *)addr) = value;
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}
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/** Writes an 8 bit value to a memory mapped IO device (ROM code version).
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*
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* @param value The 8 bit value to write.
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* @param addr The memory address to write to.
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*/
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static inline void __mmio_write_byte(uint32_t value, void *addr)
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{
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*((volatile uint8_t *)addr) = value;
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}
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/** Reads a 32 bit value from a memory mapped IO device (ROM code version).
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*
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* @param addr The memory address to read from.
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*
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* @return The 32 bit value read from the given address.
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*/
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static inline uint32_t __mmio_read_long(void *addr)
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{
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return *((volatile uint32_t *)addr);
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}
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/** Reads a 16 bit value from a memory mapped IO device (ROM code version).
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*
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* @param addr The memory address to read from.
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*
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* @return The 16 bit value read from the given address.
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*/
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static inline uint16_t __mmio_read_word(void *addr)
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{
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return *((volatile uint16_t *)addr);
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}
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/** Reads an 8 bit value from a memory mapped IO device (ROM code version).
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*
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* @param addr The memory address to read from.
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*
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* @return The 32 16 value read from the given address.
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*/
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static inline uint8_t __mmio_read_byte(void *addr)
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{
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return *((volatile uint8_t *)addr);
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}
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/** Reads a 32 Bit memory mapped IO register, mask it and write it back into
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* memory mapped IO register.
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*
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* @param addr The address of the memory mapped IO register.
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* @param mask The mask to apply to the value read.
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* @param value The 32 bit value to write.
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*/
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static inline void setl(void *addr, uint32_t mask, uint32_t value)
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{
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mmio_write_long((mmio_read_long(addr) & ~mask) | value, addr);
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}
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/** Reads a 16 Bit memory mapped IO register, mask it and write it back into
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* memory mapped IO register.
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*
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* @param addr The address of the memory mapped IO register.
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* @param mask The mask to apply to the value read.
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* @param value The 16 bit value to write.
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*/
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static inline void setw(void *addr, uint32_t mask, uint32_t value)
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{
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mmio_write_word((mmio_read_word(addr) & ~mask) | value, addr);
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}
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/** Reads a 8 Bit memory mapped IO register, mask it and write it back into
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* memory mapped IO register.
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*
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* @param addr The address of the memory mapped IO register.
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* @param mask The mask to apply to the value read.
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* @param value The 8 bit value to write.
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*/
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static inline void setb(void *addr, uint32_t mask, uint32_t value)
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{
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mmio_write_byte((mmio_read_byte(addr) & ~mask) | value, addr);
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}
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/* MMIO memory access types */
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enum mem_io_type {
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HV_MEM_IO_READ = 0,
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HV_MEM_IO_WRITE,
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};
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/* MMIO emulation related structures */
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#define MMIO_TRANS_VALID 1
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#define MMIO_TRANS_INVALID 0
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struct mem_io {
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uint64_t paddr; /* Physical address being accessed */
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enum mem_io_type read_write; /* 0 = read / 1 = write operation */
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uint8_t access_size; /* Access size being emulated */
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uint8_t sign_extend_read; /* 1 if sign extension required for read */
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uint64_t value; /* Value read or value to write */
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uint8_t mmio_status; /* Indicates if this MMIO transaction is valid */
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/* Used to store emulation context for this mmio transaction */
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void *private_data;
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};
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#endif /* _IO_H defined */
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