561 lines
28 KiB
C
561 lines
28 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MSR_H
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#define MSR_H
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/* architectural (common) MSRs */
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#define MSR_IA32_P5_MC_ADDR 0x00000000U
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/* Machine check address for MC exception handler */
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#define MSR_IA32_P5_MC_TYPE 0x00000001U
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/* Machine check error type for MC exception handler */
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#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006U
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/* System coherence line size for MWAIT/MONITOR */
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#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010U /* TSC as MSR */
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#define MSR_IA32_PLATFORM_ID 0x00000017U /* Platform ID */
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#define MSR_IA32_APIC_BASE 0x0000001BU
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/* Information about LAPIC */
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#define MSR_IA32_FEATURE_CONTROL 0x0000003AU
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/* Speculation Control */
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#define MSR_IA32_SPEC_CTRL 0x00000048U
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/* Prediction Command */
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#define MSR_IA32_PRED_CMD 0x00000049U
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/* Control Features in Intel 64 processor */
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#define MSR_IA32_ADJUST_TSC 0x0000003BU /* Adjust TSC value */
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#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079U
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/* BIOS update trigger */
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#define MSR_IA32_BIOS_SIGN_ID 0x0000008BU
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/* BIOS update signature */
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#define MSR_IA32_SMM_MONITOR_CTL 0x0000009BU
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/* SMM monitor configuration */
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#define MSR_IA32_PMC0 0x000000C1U
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/* General performance counter 0 */
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#define MSR_IA32_PMC1 0x000000C2U
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/* General performance counter 1 */
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#define MSR_IA32_PMC2 0x000000C3U
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/* General performance counter 2 */
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#define MSR_IA32_PMC3 0x000000C4U
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/* General performance counter 3 */
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#define MSR_IA32_MPERF 0x000000E7U
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/* Max. qualified performance clock counter */
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#define MSR_IA32_APERF 0x000000E8U
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/* Actual performance clock counter */
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#define MSR_IA32_MTRR_CAP 0x000000FEU /* MTRR capability */
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#define MSR_IA32_SYSENTER_CS 0x00000174U /* CS for sysenter */
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#define MSR_IA32_SYSENTER_ESP 0x00000175U /* ESP for sysenter */
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#define MSR_IA32_SYSENTER_EIP 0x00000176U /* EIP for sysenter */
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#define MSR_IA32_MCG_CAP 0x00000179U
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/* Global machine check capability */
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#define MSR_IA32_MCG_STATUS 0x0000017AU
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/* Global machine check status */
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#define MSR_IA32_MCG_CTL 0x0000017BU
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/* Global machine check control */
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#define MSR_IA32_PERFEVTSEL0 0x00000186U
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/* Performance Event Select Register 0 */
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#define MSR_IA32_PERFEVTSEL1 0x00000187U
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/* Performance Event Select Register 1 */
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#define MSR_IA32_PERFEVTSEL2 0x00000188U
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/* Performance Event Select Register 2 */
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#define MSR_IA32_PERFEVTSEL3 0x00000189U
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/* Performance Event Select Register 3 */
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#define MSR_IA32_PERF_STATUS 0x00000198U
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/* Current performance state */
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#define MSR_IA32_PERF_CTL 0x00000199U
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/* Performance control */
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#define MSR_IA32_CLOCK_MODULATION 0x0000019AU
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/* Clock modulation control */
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#define MSR_IA32_THERM_INTERRUPT 0x0000019BU
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/* Thermal interrupt control */
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#define MSR_IA32_THERM_STATUS 0x0000019CU
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/* Thermal status information */
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#define MSR_IA32_MISC_ENABLE 0x000001A0U
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/* Enable misc. processor features */
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0U
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/* Performance energy bias hint */
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#define MSR_IA32_DEBUGCTL 0x000001D9U
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/* Trace/Profile resource control */
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#define MSR_IA32_SMRR_PHYSBASE 0x000001F2U /* SMRR base address */
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#define MSR_IA32_SMRR_PHYSMASK 0x000001F3U /* SMRR range mask */
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#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8U /* DCA capability */
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#define MSR_IA32_CPU_DCA_CAP 0x000001F9U
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/* Prefetch hint type capability */
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#define MSR_IA32_DCA_0_CAP 0x000001FAU
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/* DCA type 0 status/control */
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#define MSR_IA32_MTRR_PHYSBASE_0 0x00000200U
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/* variable range MTRR base 0 */
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#define MSR_IA32_MTRR_PHYSMASK_0 0x00000201U
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/* variable range MTRR mask 0 */
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#define MSR_IA32_MTRR_PHYSBASE_1 0x00000202U
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/* variable range MTRR base 1 */
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#define MSR_IA32_MTRR_PHYSMASK_1 0x00000203U
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/* variable range MTRR mask 1 */
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#define MSR_IA32_MTRR_PHYSBASE_2 0x00000204U
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/* variable range MTRR base 2 */
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#define MSR_IA32_MTRR_PHYSMASK_2 0x00000205U
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/* variable range MTRR mask 2 */
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#define MSR_IA32_MTRR_PHYSBASE_3 0x00000206U
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/* variable range MTRR base 3 */
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#define MSR_IA32_MTRR_PHYSMASK_3 0x00000207U
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/* variable range MTRR mask 3 */
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#define MSR_IA32_MTRR_PHYSBASE_4 0x00000208U
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/* variable range MTRR base 4 */
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#define MSR_IA32_MTRR_PHYSMASK_4 0x00000209U
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/* variable range MTRR mask 4 */
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#define MSR_IA32_MTRR_PHYSBASE_5 0x0000020AU
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/* variable range MTRR base 5 */
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#define MSR_IA32_MTRR_PHYSMASK_5 0x0000020BU
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/* variable range MTRR mask 5 */
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#define MSR_IA32_MTRR_PHYSBASE_6 0x0000020CU
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/* variable range MTRR base 6 */
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#define MSR_IA32_MTRR_PHYSMASK_6 0x0000020DU
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/* variable range MTRR mask 6 */
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#define MSR_IA32_MTRR_PHYSBASE_7 0x0000020EU
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/* variable range MTRR base 7 */
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#define MSR_IA32_MTRR_PHYSMASK_7 0x0000020FU
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/* variable range MTRR mask 7 */
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#define MSR_IA32_MTRR_PHYSBASE_8 0x00000210U
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/* variable range MTRR base 8 */
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#define MSR_IA32_MTRR_PHYSMASK_8 0x00000211U
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/* variable range MTRR mask 8 */
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#define MSR_IA32_MTRR_PHYSBASE_9 0x00000212U
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/* variable range MTRR base 9 */
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#define MSR_IA32_MTRR_PHYSMASK_9 0x00000213U
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/* variable range MTRR mask 9 */
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#define MSR_IA32_MTRR_FIX64K_00000 0x00000250U
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/* fixed range MTRR 16K/0x00000 */
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#define MSR_IA32_MTRR_FIX16K_80000 0x00000258U
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/* fixed range MTRR 16K/0x80000 */
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#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259U
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/* fixed range MTRR 16K/0xA0000 */
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#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268U
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/* fixed range MTRR 4K/0xC0000 */
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#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269U
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/* fixed range MTRR 4K/0xC8000 */
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#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026AU
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/* fixed range MTRR 4K/0xD0000 */
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#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026BU
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/* fixed range MTRR 4K/0xD8000 */
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#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026CU
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/* fixed range MTRR 4K/0xE0000 */
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#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026DU
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/* fixed range MTRR 4K/0xE8000 */
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#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026EU
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/* fixed range MTRR 4K/0xF0000 */
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#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026FU
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/* fixed range MTRR 4K/0xF8000 */
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#define MSR_IA32_PAT 0x00000277U /* PAT */
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#define MSR_IA32_MC0_CTL2 0x00000280U
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/* Corrected error count threshold 0 */
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#define MSR_IA32_MC1_CTL2 0x00000281U
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/* Corrected error count threshold 1 */
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#define MSR_IA32_MC2_CTL2 0x00000282U
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/* Corrected error count threshold 2 */
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#define MSR_IA32_MC3_CTL2 0x00000283U
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/* Corrected error count threshold 3 */
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#define MSR_IA32_MC4_CTL2 0x00000284U
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/* Corrected error count threshold 4 */
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#define MSR_IA32_MC5_CTL2 0x00000285U
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/* Corrected error count threshold 5 */
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#define MSR_IA32_MC6_CTL2 0x00000286U
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/* Corrected error count threshold 6 */
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#define MSR_IA32_MC7_CTL2 0x00000287U
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/* Corrected error count threshold 7 */
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#define MSR_IA32_MC8_CTL2 0x00000288U
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/* Corrected error count threshold 8 */
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#define MSR_IA32_MC9_CTL2 0x00000289U
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/* Corrected error count threshold 9 */
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#define MSR_IA32_MC10_CTL2 0x0000028AU
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/* Corrected error count threshold 10 */
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#define MSR_IA32_MC11_CTL2 0x0000028BU
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/* Corrected error count threshold 11 */
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#define MSR_IA32_MC12_CTL2 0x0000028CU
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/* Corrected error count threshold 12 */
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#define MSR_IA32_MC13_CTL2 0x0000028DU
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/* Corrected error count threshold 13 */
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#define MSR_IA32_MC14_CTL2 0x0000028EU
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/* Corrected error count threshold 14 */
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#define MSR_IA32_MC15_CTL2 0x0000028FU
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/* Corrected error count threshold 15 */
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#define MSR_IA32_MC16_CTL2 0x00000290U
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/* Corrected error count threshold 16 */
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#define MSR_IA32_MC17_CTL2 0x00000291U
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/* Corrected error count threshold 17 */
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#define MSR_IA32_MC18_CTL2 0x00000292U
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/* Corrected error count threshold 18 */
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#define MSR_IA32_MC19_CTL2 0x00000293U
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/* Corrected error count threshold 19 */
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#define MSR_IA32_MC20_CTL2 0x00000294U
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/* Corrected error count threshold 20 */
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#define MSR_IA32_MC21_CTL2 0x00000295U
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/* Corrected error count threshold 21 */
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#define MSR_IA32_MTRR_DEF_TYPE 0x000002FFU
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/* Default memory type/MTRR control */
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#define MSR_IA32_FIXED_CTR0 0x00000309U
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/* Fixed-function performance counter 0 */
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#define MSR_IA32_FIXED_CTR1 0x0000030AU
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/* Fixed-function performance counter 1 */
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#define MSR_IA32_FIXED_CTR2 0x0000030BU
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/* Fixed-function performance counter 2 */
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#define MSR_IA32_PERF_CAPABILITIES 0x00000345U
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/* Performance capability */
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#define MSR_IA32_FIXED_CTR_CTL 0x0000038DU
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/* Fixed-function performance counter control */
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#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038EU
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/* Global performance counter status */
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#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038FU
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/* Global performance counter control */
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#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390U
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/* Global performance counter overflow control */
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#define MSR_IA32_PEBS_ENABLE 0x000003F1U /* PEBS control */
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#define MSR_IA32_MC0_CTL 0x00000400U /* MC 0 control */
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#define MSR_IA32_MC0_STATUS 0x00000401U /* MC 0 status */
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#define MSR_IA32_MC0_ADDR 0x00000402U /* MC 0 address */
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#define MSR_IA32_MC0_MISC 0x00000403U /* MC 0 misc. */
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#define MSR_IA32_MC1_CTL 0x00000404U /* MC 1 control */
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#define MSR_IA32_MC1_STATUS 0x00000405U /* MC 1 status */
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#define MSR_IA32_MC1_ADDR 0x00000406U /* MC 1 address */
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#define MSR_IA32_MC1_MISC 0x00000407U /* MC 1 misc. */
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#define MSR_IA32_MC2_CTL 0x00000408U /* MC 2 control */
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#define MSR_IA32_MC2_STATUS 0x00000409U /* MC 2 status */
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#define MSR_IA32_MC2_ADDR 0x0000040AU /* MC 2 address */
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#define MSR_IA32_MC2_MISC 0x0000040BU /* MC 2 misc. */
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#define MSR_IA32_MC3_CTL 0x0000040CU /* MC 3 control */
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#define MSR_IA32_MC3_STATUS 0x0000040DU /* MC 3 status */
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#define MSR_IA32_MC3_ADDR 0x0000040EU /* MC 3 address */
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#define MSR_IA32_MC3_MISC 0x0000040FU /* MC 3 misc. */
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#define MSR_IA32_MC4_CTL 0x00000410U /* MC 4 control */
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#define MSR_IA32_MC4_STATUS 0x00000411U /* MC 4 status */
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#define MSR_IA32_MC4_ADDR 0x00000412U /* MC 4 address */
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#define MSR_IA32_MC4_MISC 0x00000413U /* MC 4 misc. */
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#define MSR_IA32_MC5_CTL 0x00000414U /* MC 5 control */
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#define MSR_IA32_MC5_STATUS 0x00000415U /* MC 5 status */
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#define MSR_IA32_MC5_ADDR 0x00000416U /* MC 5 address */
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#define MSR_IA32_MC5_MISC 0x00000417U /* MC 5 misc. */
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#define MSR_IA32_MC6_CTL 0x00000418U /* MC 6 control */
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#define MSR_IA32_MC6_STATUS 0x00000419U /* MC 6 status */
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#define MSR_IA32_MC6_ADDR 0x0000041AU /* MC 6 address */
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#define MSR_IA32_MC6_MISC 0x0000041BU /* MC 6 misc. */
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#define MSR_IA32_MC7_CTL 0x0000041CU /* MC 7 control */
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#define MSR_IA32_MC7_STATUS 0x0000041DU /* MC 7 status */
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#define MSR_IA32_MC7_ADDR 0x0000041EU /* MC 7 address */
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#define MSR_IA32_MC7_MISC 0x0000041FU /* MC 7 misc. */
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#define MSR_IA32_MC8_CTL 0x00000420U /* MC 8 control */
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#define MSR_IA32_MC8_STATUS 0x00000421U /* MC 8 status */
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#define MSR_IA32_MC8_ADDR 0x00000422U /* MC 8 address */
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#define MSR_IA32_MC8_MISC 0x00000423U /* MC 8 misc. */
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#define MSR_IA32_MC9_CTL 0x00000424U /* MC 9 control */
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#define MSR_IA32_MC9_STATUS 0x00000425U /* MC 9 status */
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#define MSR_IA32_MC9_ADDR 0x00000426U /* MC 9 address */
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#define MSR_IA32_MC9_MISC 0x00000427U /* MC 9 misc. */
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#define MSR_IA32_MC10_CTL 0x00000428U /* MC 10 control */
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#define MSR_IA32_MC10_STATUS 0x00000429U /* MC 10 status */
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#define MSR_IA32_MC10_ADDR 0x0000042AU /* MC 10 address */
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#define MSR_IA32_MC10_MISC 0x0000042BU /* MC 10 misc. */
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#define MSR_IA32_MC11_CTL 0x0000042CU /* MC 11 control */
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#define MSR_IA32_MC11_STATUS 0x0000042DU /* MC 11 status */
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#define MSR_IA32_MC11_ADDR 0x0000042EU /* MC 11 address */
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#define MSR_IA32_MC11_MISC 0x0000042FU /* MC 11 misc. */
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#define MSR_IA32_MC12_CTL 0x00000430U /* MC 12 control */
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#define MSR_IA32_MC12_STATUS 0x00000431U /* MC 12 status */
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#define MSR_IA32_MC12_ADDR 0x00000432U /* MC 12 address */
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#define MSR_IA32_MC12_MISC 0x00000433U /* MC 12 misc. */
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#define MSR_IA32_MC13_CTL 0x00000434U /* MC 13 control */
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#define MSR_IA32_MC13_STATUS 0x00000435U /* MC 13 status */
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#define MSR_IA32_MC13_ADDR 0x00000436U /* MC 13 address */
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#define MSR_IA32_MC13_MISC 0x00000437U /* MC 13 misc. */
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#define MSR_IA32_MC14_CTL 0x00000438U /* MC 14 control */
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#define MSR_IA32_MC14_STATUS 0x00000439U /* MC 14 status */
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#define MSR_IA32_MC14_ADDR 0x0000043AU /* MC 14 address */
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#define MSR_IA32_MC14_MISC 0x0000043BU /* MC 14 misc. */
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#define MSR_IA32_MC15_CTL 0x0000043CU /* MC 15 control */
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#define MSR_IA32_MC15_STATUS 0x0000043DU /* MC 15 status */
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#define MSR_IA32_MC15_ADDR 0x0000043EU /* MC 15 address */
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#define MSR_IA32_MC15_MISC 0x0000043FU /* MC 15 misc. */
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#define MSR_IA32_MC16_CTL 0x00000440U /* MC 16 control */
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#define MSR_IA32_MC16_STATUS 0x00000441U /* MC 16 status */
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#define MSR_IA32_MC16_ADDR 0x00000442U /* MC 16 address */
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#define MSR_IA32_MC16_MISC 0x00000443U /* MC 16 misc. */
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#define MSR_IA32_MC17_CTL 0x00000444U /* MC 17 control */
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#define MSR_IA32_MC17_STATUS 0x00000445U /* MC 17 status */
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#define MSR_IA32_MC17_ADDR 0x00000446U /* MC 17 address */
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#define MSR_IA32_MC17_MISC 0x00000447U /* MC 17 misc. */
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#define MSR_IA32_MC18_CTL 0x00000448U /* MC 18 control */
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#define MSR_IA32_MC18_STATUS 0x00000449U /* MC 18 status */
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#define MSR_IA32_MC18_ADDR 0x0000044AU /* MC 18 address */
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#define MSR_IA32_MC18_MISC 0x0000044BU /* MC 18 misc. */
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#define MSR_IA32_MC19_CTL 0x0000044CU /* MC 19 control */
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#define MSR_IA32_MC19_STATUS 0x0000044DU /* MC 19 status */
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#define MSR_IA32_MC19_ADDR 0x0000044EU /* MC 19 address */
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#define MSR_IA32_MC19_MISC 0x0000044FU /* MC 19 misc. */
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#define MSR_IA32_MC20_CTL 0x00000450U /* MC 20 control */
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#define MSR_IA32_MC20_STATUS 0x00000451U /* MC 20 status */
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#define MSR_IA32_MC20_ADDR 0x00000452U /* MC 20 address */
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#define MSR_IA32_MC20_MISC 0x00000453U /* MC 20 misc. */
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#define MSR_IA32_MC21_CTL 0x00000454U /* MC 21 control */
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#define MSR_IA32_MC21_STATUS 0x00000455U /* MC 21 status */
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#define MSR_IA32_MC21_ADDR 0x00000456U /* MC 21 address */
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#define MSR_IA32_MC21_MISC 0x00000457U /* MC 21 misc. */
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#define MSR_IA32_VMX_BASIC 0x00000480U
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/* Capability reporting register basic VMX capabilities */
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#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481U
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/* Capability reporting register pin based VM execution controls */
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#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482U
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/* Capability reporting register primary processor based VM execution controls*/
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#define MSR_IA32_VMX_EXIT_CTLS 0x00000483U
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/* Capability reporting register VM exit controls */
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#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484U
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/* Capability reporting register VM entry controls */
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#define MSR_IA32_VMX_MISC 0x00000485U
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/* Reporting register misc. VMX capabilities */
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#define MSR_IA32_VMX_CR0_FIXED0 0x00000486U
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/* Capability reporting register of CR0 bits fixed to 0 */
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#define MSR_IA32_VMX_CR0_FIXED1 0x00000487U
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/* Capability reporting register of CR0 bits fixed to 1 */
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#define MSR_IA32_VMX_CR4_FIXED0 0x00000488U
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/* Capability reporting register of CR4 bits fixed to 0 */
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#define MSR_IA32_VMX_CR4_FIXED1 0x00000489U
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/* Capability reporting register of CR4 bits fixed to 1 */
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#define MSR_IA32_VMX_VMCS_ENUM 0x0000048AU
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/* Capability reporting register of VMCS field enumeration */
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#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048BU
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/* Capability reporting register of secondary processor based VM execution
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* controls
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*/
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#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048CU
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/* Capability reporting register of EPT and VPID */
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#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048DU
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/* Capability reporting register of pin based VM execution flex controls */
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#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048EU
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/* Capability reporting register of primary processor based VM execution flex
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* controls
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*/
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#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048FU
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/* Capability reporting register of VM exit flex controls */
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#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490U
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/* Capability reporting register of VM entry flex controls */
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#define MSR_IA32_DS_AREA 0x00000600U /* DS save area */
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/* APIC TSC deadline MSR */
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#define MSR_IA32_TSC_DEADLINE 0x000006E0U
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#define MSR_IA32_EXT_XAPICID 0x00000802U /* x2APIC ID */
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#define MSR_IA32_EXT_APIC_VERSION 0x00000803U /* x2APIC version */
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#define MSR_IA32_EXT_APIC_TPR 0x00000808U
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/* x2APIC task priority */
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#define MSR_IA32_EXT_APIC_PPR 0x0000080AU
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/* x2APIC processor priority */
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#define MSR_IA32_EXT_APIC_EOI 0x0000080BU /* x2APIC EOI */
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#define MSR_IA32_EXT_APIC_LDR 0x0000080DU
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/* x2APIC logical destination */
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#define MSR_IA32_EXT_APIC_SIVR 0x0000080FU
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/* x2APIC spurious interrupt vector */
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#define MSR_IA32_EXT_APIC_ISR0 0x00000810U
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/* x2APIC in-service register 0 */
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#define MSR_IA32_EXT_APIC_ISR1 0x00000811U
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/* x2APIC in-service register 1 */
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#define MSR_IA32_EXT_APIC_ISR2 0x00000812U
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/* x2APIC in-service register 2 */
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#define MSR_IA32_EXT_APIC_ISR3 0x00000813U
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/* x2APIC in-service register 3 */
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#define MSR_IA32_EXT_APIC_ISR4 0x00000814U
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/* x2APIC in-service register 4 */
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#define MSR_IA32_EXT_APIC_ISR5 0x00000815U
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/* x2APIC in-service register 5 */
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#define MSR_IA32_EXT_APIC_ISR6 0x00000816U
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/* x2APIC in-service register 6 */
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#define MSR_IA32_EXT_APIC_ISR7 0x00000817U
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/* x2APIC in-service register 7 */
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#define MSR_IA32_EXT_APIC_TMR0 0x00000818U
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/* x2APIC trigger mode register 0 */
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#define MSR_IA32_EXT_APIC_TMR1 0x00000819U
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/* x2APIC trigger mode register 1 */
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#define MSR_IA32_EXT_APIC_TMR2 0x0000081AU
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/* x2APIC trigger mode register 2 */
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#define MSR_IA32_EXT_APIC_TMR3 0x0000081BU
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/* x2APIC trigger mode register 3 */
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#define MSR_IA32_EXT_APIC_TMR4 0x0000081CU
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/* x2APIC trigger mode register 4 */
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#define MSR_IA32_EXT_APIC_TMR5 0x0000081DU
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/* x2APIC trigger mode register 5 */
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#define MSR_IA32_EXT_APIC_TMR6 0x0000081EU
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/* x2APIC trigger mode register 6 */
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#define MSR_IA32_EXT_APIC_TMR7 0x0000081FU
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/* x2APIC trigger mode register 7 */
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#define MSR_IA32_EXT_APIC_IRR0 0x00000820U
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/* x2APIC interrupt request register 0 */
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#define MSR_IA32_EXT_APIC_IRR1 0x00000821U
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/* x2APIC interrupt request register 1 */
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#define MSR_IA32_EXT_APIC_IRR2 0x00000822U
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/* x2APIC interrupt request register 2 */
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#define MSR_IA32_EXT_APIC_IRR3 0x00000823U
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/* x2APIC interrupt request register 3 */
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#define MSR_IA32_EXT_APIC_IRR4 0x00000824U
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/* x2APIC interrupt request register 4 */
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#define MSR_IA32_EXT_APIC_IRR5 0x00000825U
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/* x2APIC interrupt request register 5 */
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#define MSR_IA32_EXT_APIC_IRR6 0x00000826U
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/* x2APIC interrupt request register 6 */
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#define MSR_IA32_EXT_APIC_IRR7 0x00000827U
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/* x2APIC interrupt request register 7 */
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#define MSR_IA32_EXT_APIC_ESR 0x00000828U
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/* x2APIC error status */
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#define MSR_IA32_EXT_APIC_LVT_CMCI 0x0000082FU
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/* x2APIC LVT corrected machine check interrupt register */
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#define MSR_IA32_EXT_APIC_ICR 0x00000830U
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/* x2APIC interrupt command register */
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#define MSR_IA32_EXT_APIC_LVT_TIMER 0x00000832U
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/* x2APIC LVT timer interrupt register */
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#define MSR_IA32_EXT_APIC_LVT_THERMAL 0x00000833U
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/* x2APIC LVT thermal sensor interrupt register */
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#define MSR_IA32_EXT_APIC_LVT_PMI 0x00000834U
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/* x2APIC LVT performance monitor interrupt register */
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#define MSR_IA32_EXT_APIC_LVT_LINT0 0x00000835U
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/* x2APIC LVT LINT0 register */
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#define MSR_IA32_EXT_APIC_LVT_LINT1 0x00000836U
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/* x2APIC LVT LINT1 register */
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#define MSR_IA32_EXT_APIC_LVT_ERROR 0x00000837U
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/* x2APIC LVT error register */
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#define MSR_IA32_EXT_APIC_INIT_COUNT 0x00000838U
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/* x2APIC initial count register */
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#define MSR_IA32_EXT_APIC_CUR_COUNT 0x00000839U
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/* x2APIC current count register */
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#define MSR_IA32_EXT_APIC_DIV_CONF 0x0000083EU
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/* x2APIC divide configuration register */
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#define MSR_IA32_EXT_APIC_SELF_IPI 0x0000083FU
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/* x2APIC self IPI register */
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#define MSR_IA32_EFER 0xC0000080U
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/* Extended feature enables */
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#define MSR_IA32_STAR 0xC0000081U
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/* System call target address */
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#define MSR_IA32_LSTAR 0xC0000082U
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/* IA-32e mode system call target address */
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#define MSR_IA32_FMASK 0xC0000084U
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/* System call flag mask */
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#define MSR_IA32_FS_BASE 0xC0000100U
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/* Map of BASE address of FS */
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#define MSR_IA32_GS_BASE 0xC0000101U
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/* Map of BASE address of GS */
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#define MSR_IA32_KERNEL_GS_BASE 0xC0000102U
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/* Swap target of BASE address of GS */
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#define MSR_IA32_TSC_AUX 0xC0000103U /* Auxiliary TSC */
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/* ATOM specific MSRs */
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#define MSR_ATOM_EBL_CR_POWERON 0x0000002AU
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/* Processor hard power-on configuration */
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#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040U
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/* Last branch record 0 from IP */
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#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041U
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/* Last branch record 1 from IP */
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#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042U
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/* Last branch record 2 from IP */
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#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043U
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/* Last branch record 3 from IP */
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#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044U
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/* Last branch record 4 from IP */
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#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045U
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/* Last branch record 5 from IP */
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#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046U
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/* Last branch record 6 from IP */
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#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047U
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/* Last branch record 7 from IP */
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#define MSR_ATOM_LASTBRANCH_0_TO_LIP 0x00000060U
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/* Last branch record 0 to IP */
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#define MSR_ATOM_LASTBRANCH_1_TO_LIP 0x00000061U
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/* Last branch record 1 to IP */
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#define MSR_ATOM_LASTBRANCH_2_TO_LIP 0x00000062U
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/* Last branch record 2 to IP */
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#define MSR_ATOM_LASTBRANCH_3_TO_LIP 0x00000063U
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/* Last branch record 3 to IP */
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#define MSR_ATOM_LASTBRANCH_4_TO_LIP 0x00000064U
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/* Last branch record 4 to IP */
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#define MSR_ATOM_LASTBRANCH_5_TO_LIP 0x00000065U
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/* Last branch record 5 to IP */
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#define MSR_ATOM_LASTBRANCH_6_TO_LIP 0x00000066U
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/* Last branch record 6 to IP */
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#define MSR_ATOM_LASTBRANCH_7_TO_LIP 0x00000067U
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/* Last branch record 7 to IP */
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#define MSR_ATOM_FSB_FREQ 0x000000CDU /* Scalable bus speed */
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#define MSR_PLATFORM_INFO 0x000000CEU
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/* Maximum resolved bus ratio */
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#define MSR_ATOM_BBL_CR_CTL3 0x0000011EU /* L2 hardware enabled */
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#define MSR_ATOM_THERM2_CTL 0x0000019DU
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/* Mode of automatic thermal monitor */
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#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9U
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/* Last branch record stack TOS */
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#define MSR_ATOM_LER_FROM_LIP 0x000001DDU
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/* Last exception record from linear IP */
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#define MSR_ATOM_LER_TO_LIP 0x000001DEU
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/* Last exception record to linear IP */
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/* LINCROFT specific MSRs */
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#define MSR_LNC_BIOS_CACHE_AS_RAM 0x000002E0U /* Configure CAR */
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/* EFER bits */
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#define MSR_IA32_EFER_SCE_BIT (1UL<<0U)
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#define MSR_IA32_EFER_LME_BIT (1UL<<8U) /* IA32e mode enable */
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#define MSR_IA32_EFER_LMA_BIT (1UL<<10U) /* IA32e mode active */
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#define MSR_IA32_EFER_NXE_BIT (1UL<<11U)
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/* FEATURE CONTROL bits */
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#define MSR_IA32_FEATURE_CONTROL_LOCK (1U<<0)
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#define MSR_IA32_FEATURE_CONTROL_VMX_SMX (1U<<1)
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#define MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX (1U<<2)
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/* PAT memory type definitions */
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#define PAT_MEM_TYPE_UC 0x00UL /* uncached */
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#define PAT_MEM_TYPE_WC 0x01UL /* write combining */
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#define PAT_MEM_TYPE_WT 0x04UL /* write through */
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#define PAT_MEM_TYPE_WP 0x05UL /* write protected */
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#define PAT_MEM_TYPE_WB 0x06UL /* writeback */
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#define PAT_MEM_TYPE_UCM 0x07UL /* uncached minus */
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#define PAT_MEM_TYPE_INVALID(x) (((x) != PAT_MEM_TYPE_UC) && \
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((x) != PAT_MEM_TYPE_WC) && \
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((x) != PAT_MEM_TYPE_WT) && \
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((x) != PAT_MEM_TYPE_WP) && \
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((x) != PAT_MEM_TYPE_WB) && \
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((x) != PAT_MEM_TYPE_UCM))
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/* 5 high-order bits in every field are reserved */
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#define PAT_FIELD_RSV_BITS (0xF8U)
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#define PAT_POWER_ON_VALUE (PAT_MEM_TYPE_WB + \
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(PAT_MEM_TYPE_WT << 8U) + \
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(PAT_MEM_TYPE_UCM << 16U) + \
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(PAT_MEM_TYPE_UC << 24U) + \
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(PAT_MEM_TYPE_WB << 32U) + \
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(PAT_MEM_TYPE_WT << 40U) + \
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(PAT_MEM_TYPE_UCM << 48U) + \
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(PAT_MEM_TYPE_UC << 56U))
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#define PAT_ALL_UC_VALUE (PAT_MEM_TYPE_UC + \
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(PAT_MEM_TYPE_UC << 8U) + \
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(PAT_MEM_TYPE_UC << 16U) + \
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(PAT_MEM_TYPE_UC << 24U) + \
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(PAT_MEM_TYPE_UC << 32U) + \
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(PAT_MEM_TYPE_UC << 40U) + \
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(PAT_MEM_TYPE_UC << 48U) + \
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(PAT_MEM_TYPE_UC << 56U))
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/* MTRR memory type definitions */
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#define MTRR_MEM_TYPE_UC 0x00UL /* uncached */
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#define MTRR_MEM_TYPE_WC 0x01UL /* write combining */
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#define MTRR_MEM_TYPE_WT 0x04UL /* write through */
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#define MTRR_MEM_TYPE_WP 0x05UL /* write protected */
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#define MTRR_MEM_TYPE_WB 0x06UL /* writeback */
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/* misc. MTRR flag definitions */
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#define MTRR_ENABLE 0x800U /* MTRR enable */
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#define MTRR_FIX_ENABLE 0x400U /* fixed range MTRR enable */
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#define MTRR_VALID 0x800U /* MTRR setting is valid */
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/* SPEC & PRED bit */
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#define SPEC_ENABLE_IBRS (1U<<0)
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#define SPEC_ENABLE_STIBP (1U<<1)
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#define PRED_SET_IBPB (1U<<0)
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/* Turbo config bit */
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#define TURBO_MODE_DISABLE (1UL<<38)
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#endif /* MSR_H */
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