acrn-hypervisor/hypervisor/debug
Jason Chen CJ 3d5d6c96ec vcpu: add get/set register APIs
there will be 3 types of vcpu runtime contexts:
- runtime contexts always saved/restored during VM exit/entry, which
  include general registers rax/rcx/rdx/rbx/rbp/rsi/rdi/r8~r15, cr2 and
  msr for spectre control (ia32_spec_ctrl)
- runtime contexts on-demand cached/updated during VM exit/entry, which
  include frequently used registers rsp, rip, efer, rflags, cr0 and cr4
- runtime contexts always read/write from/to VMCS, which include left
  registers not in above

this patch add get/set register APIs for vcpu runtime contexts, and unified
the save/restore method for them according to above description.

v3:
- update vcpu_get/set_cr0/4 as unified interface to get/set guest cr0/cr4,
  use on-demand cache for reading, but always write to VMCS for writing.

v2:
- use reg_cached/reg_updated for on-demand runtime contexts
- always read/write cr3 from/to VMCS

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-07 09:55:13 +08:00
..
console.c hv:cleanup console/uart code 2018-08-02 11:25:40 +08:00
dump.c vcpu: add get/set register APIs 2018-08-07 09:55:13 +08:00
logmsg.c HV:fix rest integer violations 2018-08-02 09:51:58 +08:00
printf.c HV:fix rest integer violations 2018-08-02 09:51:58 +08:00
sbuf.c HV:fix rest integer violations 2018-08-02 09:51:58 +08:00
shell.c vcpu: add get/set register APIs 2018-08-07 09:55:13 +08:00
shell_internal.h hv: treewide: fix 'Prototype and definition name mismatch' 2018-08-06 16:04:40 +08:00
uart16550.c hv:Rename port/mmio read and write APIs 2018-08-02 14:03:38 +08:00
uart16550.h hv:cleanup console/uart code 2018-08-02 11:25:40 +08:00
vuart.c hv:cleanup console/uart code 2018-08-02 11:25:40 +08:00