141 lines
3.7 KiB
C
141 lines
3.7 KiB
C
/*
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* Copyright (c) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <logmsg.h>
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#include <pci.h>
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#include <asm/guest/vm.h>
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#include <acrn_common.h>
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#include "vroot_port.h"
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#include "vpci_priv.h"
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#define PCIE_CAP_VPOS 0x40 /* pcie capability reg position */
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#define PTM_CAP_VPOS PCI_ECAP_BASE_PTR /* ptm capability reg postion */
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static void init_vrp(struct pci_vdev *vdev)
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{
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/* vendor and device */
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pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, VRP_VENDOR);
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pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, VRP_DEVICE);
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/* status register */
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pci_vdev_write_vcfg(vdev, PCIR_STATUS, 2U, PCIM_STATUS_CAPPRESENT);
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/* rev id */
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pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0x01U);
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/* sub class */
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pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_PCI);
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/* class */
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pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE);
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/* Header Type */
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pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, PCIM_HDRTYPE_BRIDGE);
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/* capability pointer */
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pci_vdev_write_vcfg(vdev, PCIR_CAP_PTR, 1U, PCIE_CAP_VPOS);
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/* pcie capability registers */
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pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCICAP_ID, 1U, 0x10);
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pci_vdev_write_vcfg(vdev, PCIE_CAP_VPOS + PCICAP_EXP_CAP, 2U, 0x0142);
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vdev->parent_user = NULL;
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vdev->user = vdev;
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}
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static void deinit_vrp(__unused struct pci_vdev *vdev)
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{
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vdev->parent_user = NULL;
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vdev->user = NULL;
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}
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static int32_t read_vrp_cfg(const struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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*val = pci_vdev_read_vcfg(vdev, offset, bytes);
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return 0;
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}
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static int32_t write_vrp_cfg(__unused struct pci_vdev *vdev, __unused uint32_t offset,
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__unused uint32_t bytes, __unused uint32_t val)
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{
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pci_vdev_write_vcfg(vdev, offset, bytes, val);
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return 0;
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}
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/*
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* @pre vdev != NULL
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* @pre vrp_config != NULL
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*/
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static void init_ptm(struct pci_vdev *vdev, struct vrp_config *vrp_config)
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{
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/* ptm capability register */
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if (vrp_config->ptm_capable)
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{
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pci_vdev_write_vcfg(vdev, PTM_CAP_VPOS, PCI_PTM_CAP_LEN, 0x0001001f);
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pci_vdev_write_vcfg(vdev, PTM_CAP_VPOS + PCIR_PTM_CAP, PCI_PTM_CAP_LEN, 0x406);
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pci_vdev_write_vcfg(vdev, PTM_CAP_VPOS + PCIR_PTM_CTRL, PCI_PTM_CAP_LEN, 0x3);
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}
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/* emulate bus numbers */
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pci_vdev_write_vcfg(vdev, PCIR_PRIBUS_1, 1U, 0x00); /* virtual root port always connects to host bridge */
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pci_vdev_write_vcfg(vdev, PCIR_SECBUS_1, 1U, vrp_config->secondary_bus);
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pci_vdev_write_vcfg(vdev, PCIR_SUBBUS_1, 1U, vrp_config->subordinate_bus);
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}
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int32_t create_vrp(struct acrn_vm *vm, struct acrn_emul_dev *dev)
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{
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struct acrn_vm_config *vm_config = get_vm_config(vm->vm_id);
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struct acrn_vm_pci_dev_config *dev_config = NULL;
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struct pci_vdev *vdev;
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struct vrp_config *vrp_config;
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int i;
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vrp_config = (struct vrp_config*)dev->args;
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pr_acrnlog("%s: virtual root port phy_bdf=0x%x, vbdf=0x%x, vendor_id=0x%x, dev_id=0x%x,\
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primary_bus=0x%x, secondary_bus=0x%x, sub_bus=0x%x.\n",
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__func__, vrp_config->phy_bdf, dev->slot,
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dev->dev_id.fields.vendor_id, dev->dev_id.fields.device_id,
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vrp_config->primary_bus, vrp_config->secondary_bus, vrp_config->subordinate_bus);
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for (i = 0U; i < vm_config->pci_dev_num; i++) {
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dev_config = &vm_config->pci_devs[i];
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if (dev_config->vrp_sec_bus == vrp_config->secondary_bus) {
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dev_config->vbdf.value = dev->slot;
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dev_config->pbdf.value = vrp_config->phy_bdf;
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dev_config->vdev_ops = &vrp_ops;
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vdev = vpci_init_vdev(&vm->vpci, dev_config, NULL);
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init_ptm(vdev, vrp_config);
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break;
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}
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}
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return 0;
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}
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int32_t destroy_vrp(__unused struct pci_vdev *vdev)
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{
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return 0;
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}
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const struct pci_vdev_ops vrp_ops = {
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.init_vdev = init_vrp,
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.deinit_vdev = deinit_vrp,
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.write_vdev_cfg = write_vrp_cfg,
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.read_vdev_cfg = read_vrp_cfg,
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};
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