204 lines
6.8 KiB
C
204 lines
6.8 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm/guest/vm.h>
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#include <ptdev.h>
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#include <asm/guest/assign.h>
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#include <vpci.h>
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#include <asm/vtd.h>
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#include <asm/board.h>
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#include "vpci_priv.h"
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#define PER_VECTOR_MASK_CAP 0x0100U
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/* Pre-assumptions for vMSI-x on MSI emulation:
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* 1. The device is in vmsix_on_msi_devs array.
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* 2. The device should support MSI capability as well as per-vector mask
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* 3. The device doesn't support MSI-x capability.
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* 4. The device should have an unused BAR (this condition is checked inside init_vmsix_on_msi).
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* 5. HV doesn't emulate PBA according to physcial device status, the device driver should not rely on PBA
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* for functionality.
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*/
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static bool need_vmsix_on_msi_emulation(__unused struct pci_pdev *pdev, __unused uint16_t *vector_count)
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{
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bool ret = false;
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#if (MAX_VMSIX_ON_MSI_PDEVS_NUM > 0)
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uint16_t msgctrl;
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uint32_t i;
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for(i = 0U; i < MAX_VMSIX_ON_MSI_PDEVS_NUM; i++) {
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if (pdev->bdf.value == vmsix_on_msi_devs[i].bdf.value) {
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if ((pdev->msi_capoff != 0U) && (pdev->msix.capoff == 0U)) {
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msgctrl = (uint16_t)pci_pdev_read_cfg(pdev->bdf, pdev->msi_capoff + PCIR_MSI_CTRL, 2U);
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*vector_count = 1U << ((msgctrl & PCIM_MSICTRL_MMC_MASK) >> 1U);
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if ((*vector_count > 1U) && ((msgctrl & PER_VECTOR_MASK_CAP) != 0U)) {
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ret = true;
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}
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}
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break;
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}
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}
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#endif
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return ret;
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}
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void reserve_vmsix_on_msi_irtes(struct pci_pdev *pdev)
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{
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struct intr_source intr_src;
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uint16_t count = 0;
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int32_t ret;
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if (need_vmsix_on_msi_emulation(pdev, &count)) {
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intr_src.is_msi = true;
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intr_src.src.msi.value = pdev->bdf.value;
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ret = dmar_reserve_irte(&intr_src, count, &pdev->irte_start);
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if ((ret == 0) && (pdev->irte_start != INVALID_IRTE_ID)) {
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pdev->irte_count = count;
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}
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}
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}
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static inline uint32_t get_mask_bits_offset(const struct pci_vdev *vdev)
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{
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return vdev->msi.is_64bit ? (vdev->msix.capoff + 0x10U) : (vdev->msix.capoff + 0xCU);
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->pdev != NULL
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*/
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void init_vmsix_on_msi(struct pci_vdev *vdev)
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{
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struct pci_pdev *pdev = vdev->pdev;
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uint32_t i;
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/* irte_count > 1 only when the device needs vMSI-x on MSI emulation and IRTEs are reserved successfully */
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if (pdev->irte_count > 1U) {
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/* find an unused BAR */
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for (i = 0U; i < vdev->nr_bars; i++) {
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if (vdev->vbars[i].base_hpa == 0UL){
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break;
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}
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if (is_pci_mem64lo_bar(&vdev->vbars[i])) {
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i++;
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}
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}
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if (i < vdev->nr_bars) {
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vdev->msix.capoff = pdev->msi_capoff;
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vdev->msi.capoff = 0U;
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vdev->msix.is_vmsix_on_msi = true;
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/* For a device support MSI with per-vector mask, the length of MSI cap is at least 20 bytes */
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vdev->msix.caplen = MSIX_CAPLEN;
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vdev->msix.table_bar = i;
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vdev->msix.table_offset = 0U;
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vdev->msix.table_count = pdev->irte_count;
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/* capability ID */
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pci_vdev_write_vcfg(vdev, vdev->msix.capoff, 1U, 0x11U);
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/* message control, MSI-X Diabled, Function unamsked */
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pci_vdev_write_vcfg(vdev, vdev->msix.capoff + 2U, 2U, pdev->irte_count - 1U);
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/* Init MSIX table vBAR, offset is 0 */
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pci_vdev_write_vcfg(vdev, vdev->msix.capoff + 4U, 4U, i);
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/* Init PBA table vBAR, offset is 2048 */
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pci_vdev_write_vcfg(vdev, vdev->msix.capoff + 8U, 4U, 2048U + i);
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vdev->vbars[i].size = 4096U;
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vdev->vbars[i].base_hpa = 0x0UL;
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vdev->vbars[i].mask = 0xFFFFF000U & PCI_BASE_ADDRESS_MEM_MASK;
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/* fixed for memory, 32bit, non-prefetchable */
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vdev->vbars[i].bar_type.bits = PCIM_BAR_MEM_32;
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/* About MSI-x bar GPA:
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* - For Service VM: when first time init, it is programmed as 0, then OS will program
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* the value later.
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* - For Post-launched VM: The GPA is assigned by device model.
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* - For Pre-launched VM: The GPA is assigned by acrn-config tool.
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*/
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if (is_prelaunched_vm(vpci2vm(vdev->vpci))) {
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vdev->vbars[i].base_gpa = vdev->pci_dev_config->vbar_base[i];
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pci_vdev_write_vbar(vdev, i, (uint32_t)vdev->vbars[i].base_gpa);
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}
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}
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}
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}
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void write_vmsix_cap_reg_on_msi(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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uint16_t old_msgctrl, msgctrl;
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uint16_t msi_msgctrl;
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old_msgctrl = (uint16_t)pci_vdev_read_vcfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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/* Write to vdev */
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pci_vdev_write_vcfg(vdev, offset, bytes, val);
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msgctrl = (uint16_t)pci_vdev_read_vcfg(vdev, vdev->msix.capoff + PCIR_MSIX_CTRL, 2U);
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if (((old_msgctrl ^ msgctrl) & (PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK)) != 0U) {
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msi_msgctrl = (uint16_t)pci_pdev_read_cfg(vdev->pdev->bdf, offset, 2U);
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msi_msgctrl = msi_msgctrl & (~PCIM_MSICTRL_MME_MASK);
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msi_msgctrl &= ~ PCIM_MSICTRL_MSI_ENABLE;
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/* If MSI Enable is being set, make sure INTxDIS bit is set */
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if ((msgctrl & PCIM_MSIXCTRL_MSIX_ENABLE) != 0U) {
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enable_disable_pci_intx(vdev->pdev->bdf, false);
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msi_msgctrl |= (msi_msgctrl & PCIM_MSICTRL_MMC_MASK) << 3U;
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msi_msgctrl |= PCIM_MSICTRL_MSI_ENABLE;
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}
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pci_pdev_write_cfg(vdev->pdev->bdf, offset, 2U, msi_msgctrl);
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if ((msgctrl & PCIM_MSIXCTRL_FUNCTION_MASK) != 0U) {
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pci_pdev_write_cfg(vdev->pdev->bdf, get_mask_bits_offset(vdev), 4U, 0xFFFFFFFFU);
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}
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}
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}
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void remap_one_vmsix_entry_on_msi(struct pci_vdev *vdev, uint32_t index)
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{
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const struct msix_table_entry *ventry;
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uint32_t mask_bits;
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uint32_t vector_mask = 1U << index;
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struct msi_info info = {};
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union pci_bdf pbdf = vdev->pdev->bdf;
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union irte_index ir_index;
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int32_t ret = 0;
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uint32_t capoff = vdev->msix.capoff;
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mask_bits = pci_pdev_read_cfg(pbdf, get_mask_bits_offset(vdev), 4U);
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mask_bits |= vector_mask;
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pci_pdev_write_cfg(pbdf, get_mask_bits_offset(vdev), 4U, mask_bits);
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ventry = &vdev->msix.table_entries[index];
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if ((ventry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0U) {
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info.addr.full = vdev->msix.table_entries[index].addr;
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info.data.full = vdev->msix.table_entries[index].data;
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ret = ptirq_prepare_msix_remap(vpci2vm(vdev->vpci), vdev->bdf.value, pbdf.value,
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(uint16_t)index, &info, vdev->pdev->irte_start + (uint16_t)index);
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if (ret == 0) {
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if (!vdev->msix.is_vmsix_on_msi_programmed) {
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ir_index.index = vdev->pdev->irte_start;
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info.addr.ir_bits.shv = 1U;
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info.addr.ir_bits.intr_index_high = ir_index.bits.index_high;
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info.addr.ir_bits.intr_index_low = ir_index.bits.index_low;
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR, 0x4U, (uint32_t)info.addr.full);
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if (vdev->msi.is_64bit) {
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_ADDR_HIGH, 0x4U,
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(uint32_t)(info.addr.full >> 32U));
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA_64BIT, 0x2U,
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(uint16_t)info.data.full);
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} else {
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pci_pdev_write_cfg(pbdf, capoff + PCIR_MSI_DATA, 0x2U,
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(uint16_t)info.data.full);
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}
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vdev->msix.is_vmsix_on_msi_programmed = true;
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}
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mask_bits &= ~vector_mask;
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}
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}
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pci_pdev_write_cfg(pbdf, get_mask_bits_offset(vdev), 4U, mask_bits);
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}
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