336 lines
10 KiB
C
336 lines
10 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <types.h>
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#include <asm/lib/atomic.h>
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#include <asm/pgtable.h>
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#include <asm/cpu_caps.h>
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#include <asm/mmu.h>
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#include <asm/vmx.h>
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#include <reloc.h>
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#include <asm/guest/vm.h>
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#include <asm/boot/ld_sym.h>
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#include <logmsg.h>
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#include <misc_cfg.h>
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static void *ppt_mmu_pml4_addr;
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static uint8_t sanitized_page[PAGE_SIZE] __aligned(PAGE_SIZE);
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/* PPT VA and PA are identical mapping */
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#define PPT_PML4_PAGE_NUM PML4_PAGE_NUM(MAX_PHY_ADDRESS_SPACE)
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#define PPT_PDPT_PAGE_NUM PDPT_PAGE_NUM(MAX_PHY_ADDRESS_SPACE)
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/* Please refer to how the EPT_PD_PAGE_NUM was calculated */
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#define PPT_PD_PAGE_NUM (PD_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE + (MEM_4G)) + \
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CONFIG_MAX_PCI_DEV_NUM * 6U)
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#define PPT_PT_PAGE_NUM 0UL /* not support 4K granularity page mapping */
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/* must be a multiple of 64 */
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#define PPT_PAGE_NUM (roundup((PPT_PML4_PAGE_NUM + PPT_PDPT_PAGE_NUM + \
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PPT_PD_PAGE_NUM + PPT_PT_PAGE_NUM), 64U))
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static struct page ppt_pages[PPT_PAGE_NUM];
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static uint64_t ppt_page_bitmap[PPT_PAGE_NUM / 64];
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/* ppt: primary page pool */
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static struct page_pool ppt_page_pool = {
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.start_page = ppt_pages,
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.bitmap_size = PPT_PAGE_NUM / 64,
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.bitmap = ppt_page_bitmap,
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.last_hint_id = 0UL,
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.dummy_page = NULL,
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};
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/* @pre: The PPT and EPT have same page granularity */
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static inline bool ppt_large_page_support(enum _page_table_level level, __unused uint64_t prot)
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{
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bool support;
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if (level == IA32E_PD) {
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support = true;
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} else if (level == IA32E_PDPT) {
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support = pcpu_has_vmx_ept_cap(VMX_EPT_1GB_PAGE);
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} else {
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support = false;
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}
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return support;
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}
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static inline void ppt_clflush_pagewalk(const void* entry __attribute__((unused)))
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{
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}
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static inline uint64_t ppt_pgentry_present(uint64_t pte)
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{
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return pte & PAGE_PRESENT;
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}
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static inline void ppt_nop_tweak_exe_right(uint64_t *entry __attribute__((unused))) {}
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static inline void ppt_nop_recover_exe_right(uint64_t *entry __attribute__((unused))) {}
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static const struct pgtable ppt_pgtable = {
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.default_access_right = (PAGE_PRESENT | PAGE_RW | PAGE_USER),
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.pool = &ppt_page_pool,
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.large_page_support = ppt_large_page_support,
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.pgentry_present = ppt_pgentry_present,
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.clflush_pagewalk = ppt_clflush_pagewalk,
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.tweak_exe_right = ppt_nop_tweak_exe_right,
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.recover_exe_right = ppt_nop_recover_exe_right,
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};
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/*
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* @pre: the combined type and vpid is correct
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*/
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static inline void local_invvpid(uint64_t type, uint16_t vpid, uint64_t gva)
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{
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const struct invvpid_operand operand = { vpid, 0U, 0U, gva };
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if (asm_invvpid(operand, type) != 0) {
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pr_dbg("%s, failed. type = %lu, vpid = %u", __func__, type, vpid);
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}
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}
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/*
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* @pre: the combined type and EPTP is correct
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*/
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static inline void local_invept(uint64_t type, struct invept_desc desc)
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{
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if (asm_invept(type, desc) != 0) {
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pr_dbg("%s, failed. type = %lu, eptp = 0x%lx", __func__, type, desc.eptp);
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}
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}
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void flush_vpid_single(uint16_t vpid)
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{
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if (vpid != 0U) {
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local_invvpid(VMX_VPID_TYPE_SINGLE_CONTEXT, vpid, 0UL);
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}
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}
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void flush_vpid_global(void)
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{
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local_invvpid(VMX_VPID_TYPE_ALL_CONTEXT, 0U, 0UL);
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}
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void invept(const void *eptp)
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{
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struct invept_desc desc = {0};
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if (pcpu_has_vmx_ept_cap(VMX_EPT_INVEPT_SINGLE_CONTEXT)) {
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desc.eptp = hva2hpa(eptp) | (3UL << 3U) | 6UL;
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local_invept(INVEPT_TYPE_SINGLE_CONTEXT, desc);
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} else if (pcpu_has_vmx_ept_cap(VMX_EPT_INVEPT_GLOBAL_CONTEXT)) {
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local_invept(INVEPT_TYPE_ALL_CONTEXTS, desc);
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} else {
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/* Neither type of INVEPT is supported. Skip. */
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}
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}
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void enable_paging(void)
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{
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uint64_t tmp64 = 0UL;
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/*
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* Enable MSR IA32_EFER.NXE bit,to prevent
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* instruction fetching from pages with XD bit set.
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*/
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tmp64 = msr_read(MSR_IA32_EFER);
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tmp64 |= MSR_IA32_EFER_NXE_BIT;
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msr_write(MSR_IA32_EFER, tmp64);
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/* Enable Write Protect, inhibiting writing to read-only pages */
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CPU_CR_READ(cr0, &tmp64);
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CPU_CR_WRITE(cr0, tmp64 | CR0_WP);
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/* HPA->HVA is 1:1 mapping at this moment, simply treat ppt_mmu_pml4_addr as HPA. */
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CPU_CR_WRITE(cr3, ppt_mmu_pml4_addr);
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}
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void enable_smep(void)
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{
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uint64_t val64 = 0UL;
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/* Enable CR4.SMEP*/
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CPU_CR_READ(cr4, &val64);
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CPU_CR_WRITE(cr4, val64 | CR4_SMEP);
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}
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void enable_smap(void)
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{
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uint64_t val64 = 0UL;
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/* Enable CR4.SMAP*/
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CPU_CR_READ(cr4, &val64);
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CPU_CR_WRITE(cr4, val64 | CR4_SMAP);
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}
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/*
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* Clean USER bit in page table to update memory pages to be owned by hypervisor.
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*/
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void set_paging_supervisor(uint64_t base, uint64_t size)
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{
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uint64_t base_aligned;
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uint64_t size_aligned;
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uint64_t region_end = base + size;
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/*rounddown base to 2MBytes aligned.*/
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base_aligned = round_pde_down(base);
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size_aligned = region_end - base_aligned;
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pgtable_modify_or_del_map((uint64_t *)ppt_mmu_pml4_addr, base_aligned,
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round_pde_up(size_aligned), 0UL, PAGE_USER, &ppt_pgtable, MR_MODIFY);
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}
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void set_paging_nx(uint64_t base, uint64_t size)
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{
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uint64_t region_end = base + size;
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uint64_t base_aligned = round_pde_down(base);
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uint64_t size_aligned = round_pde_up(region_end - base_aligned);
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pgtable_modify_or_del_map((uint64_t *)ppt_mmu_pml4_addr,
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base_aligned, size_aligned, PAGE_NX, 0UL, &ppt_pgtable, MR_MODIFY);
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}
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void set_paging_x(uint64_t base, uint64_t size)
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{
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uint64_t region_end = base + size;
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uint64_t base_aligned = round_pde_down(base);
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uint64_t size_aligned = round_pde_up(region_end - base_aligned);
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pgtable_modify_or_del_map((uint64_t *)ppt_mmu_pml4_addr,
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base_aligned, size_aligned, 0UL, PAGE_NX, &ppt_pgtable, MR_MODIFY);
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}
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void init_paging(void)
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{
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uint64_t hv_hva;
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uint32_t i;
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uint64_t low32_max_ram = 0UL;
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uint64_t high64_max_ram = MEM_4G;
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const struct e820_entry *entry;
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uint32_t entries_count = get_e820_entries_count();
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const struct e820_entry *p_e820 = get_e820_entry();
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pr_dbg("HV MMU Initialization");
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init_sanitized_page((uint64_t *)sanitized_page, hva2hpa_early(sanitized_page));
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/* Allocate memory for Hypervisor PML4 table */
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ppt_mmu_pml4_addr = pgtable_create_root(&ppt_pgtable);
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/* Modify WB attribute for E820_TYPE_RAM */
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for (i = 0U; i < entries_count; i++) {
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entry = p_e820 + i;
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if (entry->type == E820_TYPE_RAM) {
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uint64_t end = entry->baseaddr + entry->length;
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if (end < MEM_4G) {
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low32_max_ram = max(end, low32_max_ram);
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} else {
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high64_max_ram = max(end, high64_max_ram);
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}
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}
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}
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low32_max_ram = round_pde_up(low32_max_ram);
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high64_max_ram = round_pde_down(high64_max_ram);
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/* Map [0, low32_max_ram) and [4G, high64_max_ram) RAM regions as WB attribute */
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pgtable_add_map((uint64_t *)ppt_mmu_pml4_addr, 0UL, 0UL,
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low32_max_ram, PAGE_ATTR_USER | PAGE_CACHE_WB, &ppt_pgtable);
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pgtable_add_map((uint64_t *)ppt_mmu_pml4_addr, MEM_4G, MEM_4G,
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high64_max_ram - MEM_4G, PAGE_ATTR_USER | PAGE_CACHE_WB, &ppt_pgtable);
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/* Map [low32_max_ram, 4G) and [HI_MMIO_START, HI_MMIO_END) MMIO regions as UC attribute */
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pgtable_add_map((uint64_t *)ppt_mmu_pml4_addr, low32_max_ram, low32_max_ram,
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MEM_4G - low32_max_ram, PAGE_ATTR_USER | PAGE_CACHE_UC, &ppt_pgtable);
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if ((HI_MMIO_START != ~0UL) && (HI_MMIO_END != 0UL)) {
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pgtable_add_map((uint64_t *)ppt_mmu_pml4_addr, HI_MMIO_START, HI_MMIO_START,
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(HI_MMIO_END - HI_MMIO_START), PAGE_ATTR_USER | PAGE_CACHE_UC, &ppt_pgtable);
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}
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/*
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* set the paging-structure entries' U/S flag to supervisor-mode for hypervisor owned memroy.
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* (exclude the memory reserve for trusty)
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*
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* Before the new PML4 take effect in enable_paging(), HPA->HVA is always 1:1 mapping,
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* simply treat the return value of get_hv_image_base() as HPA.
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*/
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hv_hva = get_hv_image_base();
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pgtable_modify_or_del_map((uint64_t *)ppt_mmu_pml4_addr, hv_hva & PDE_MASK,
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CONFIG_HV_RAM_SIZE + (((hv_hva & (PDE_SIZE - 1UL)) != 0UL) ? PDE_SIZE : 0UL),
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PAGE_CACHE_WB, PAGE_CACHE_MASK | PAGE_USER, &ppt_pgtable, MR_MODIFY);
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/*
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* remove 'NX' bit for pages that contain hv code section, as by default XD bit is set for
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* all pages, including pages for guests.
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*/
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pgtable_modify_or_del_map((uint64_t *)ppt_mmu_pml4_addr, round_pde_down(hv_hva),
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round_pde_up((uint64_t)&ld_text_end) - round_pde_down(hv_hva), 0UL,
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PAGE_NX, &ppt_pgtable, MR_MODIFY);
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#if (SOS_VM_NUM == 1)
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pgtable_modify_or_del_map((uint64_t *)ppt_mmu_pml4_addr, (uint64_t)get_sworld_memory_base(),
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TRUSTY_RAM_SIZE * MAX_POST_VM_NUM, PAGE_USER, 0UL, &ppt_pgtable, MR_MODIFY);
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#endif
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/* Enable paging */
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enable_paging();
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}
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void flush_tlb(uint64_t addr)
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{
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invlpg(addr);
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}
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void flush_tlb_range(uint64_t addr, uint64_t size)
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{
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uint64_t linear_addr;
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for (linear_addr = addr; linear_addr < (addr + size); linear_addr += PAGE_SIZE) {
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invlpg(linear_addr);
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}
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}
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void flush_invalidate_all_cache(void)
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{
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wbinvd();
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}
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void flush_cacheline(const volatile void *p)
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{
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clflush(p);
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}
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void flush_cache_range(const volatile void *p, uint64_t size)
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{
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uint64_t i;
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for (i = 0UL; i < size; i += CACHE_LINE_SIZE) {
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clflushopt(p + i);
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}
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}
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