acrn-hypervisor/hypervisor/include/debug
Victor Sun 4c0965d89e HV: correct ept page array usage
Currently ept_pages_info[] is initialized with first element only that force
VM of id 0 using SOS EPT pages. This is incorrect for logical partition and
hybrid scenario. Considering SOS_RAM_SIZE and UOS_RAM_SIZE are configured
separately, we should use different ept pages accordingly.

So, the PRE_VM_NUM/SOS_VM_NUM and MAX_POST_VM_NUM macros are introduced to
resolve this issue. The macros would be generated by acrn-config tool when
user configure ACRN for their specific scenario.

One more thing, that when UOS_RAM_SIZE is less then 2GB, the EPT address
range should be (4G + PLATFORM_HI_MMIO_SIZE).

Tracked-On: #4458

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-12 14:56:34 +08:00
..
console.h HV: vuart: remove console related code from vuart 2019-04-29 15:25:39 +08:00
dbg_cmd.h hv:cleanup console.h 2019-02-27 11:12:48 +08:00
dump.h hv: clean up function definitions in dump.h 2018-11-28 14:57:49 +08:00
logmsg.h hv: rename the ACRN_DBG_XXX 2020-01-14 10:21:23 +08:00
npk_log.h hv: clean up function definitions in npk_log.h 2018-11-28 14:57:49 +08:00
profiling.h profiling: split profiling_vmexit_handler into two functions 2018-12-14 08:54:30 +08:00
profiling_internal.h HV: correct ept page array usage 2020-03-12 14:56:34 +08:00
sbuf.h hv: bugfix for sbuf reset 2019-06-27 15:40:19 +08:00
shell.h hv:cleanup console.h 2019-02-27 11:12:48 +08:00
trace.h hv: clean up function definitions in trace.h 2018-11-28 14:57:49 +08:00
uart16550.h hv: pci: rename CFG read/write function for PCI-compatible Configuration Mechanism 2020-03-12 09:17:02 +08:00