262 lines
7.1 KiB
C
262 lines
7.1 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <bits.h>
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#include <msr.h>
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#include <cpu.h>
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#include <per_cpu.h>
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#include <cpu_caps.h>
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#include <lapic.h>
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union lapic_base_msr {
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uint64_t value;
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struct {
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uint32_t rsvd_1:8;
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uint32_t bsp:1;
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uint32_t rsvd_2:1;
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uint32_t x2APIC_enable:1;
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uint32_t xAPIC_enable:1;
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uint32_t lapic_paddr:24;
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uint32_t rsvd_3:28;
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} fields;
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};
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static struct lapic_regs saved_lapic_regs;
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static union lapic_base_msr saved_lapic_base_msr;
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static void clear_lapic_isr(void)
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{
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uint32_t i;
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uint32_t isr_reg;
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/* This is a Intel recommended procedure and assures that the processor
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* does not get hung up due to already set "in-service" interrupts left
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* over from the boot loader environment. This actually occurs in real
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* life, therefore we will ensure all the in-service bits are clear.
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*/
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for (isr_reg = MSR_IA32_EXT_APIC_ISR7; isr_reg >= MSR_IA32_EXT_APIC_ISR0; isr_reg--) {
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for (i = 0U; i < 32U; i++) {
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if (msr_read(isr_reg) != 0U) {
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msr_write(MSR_IA32_EXT_APIC_EOI, 0U);
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} else {
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break;
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}
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}
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}
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}
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void early_init_lapic(void)
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{
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union lapic_base_msr base;
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/* Get local APIC base address */
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base.value = msr_read(MSR_IA32_APIC_BASE);
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/* Enable LAPIC in x2APIC mode*/
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/* The following sequence of msr writes to enable x2APIC
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* will work irrespective of the state of LAPIC
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* left by BIOS
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*/
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/* Step1: Enable LAPIC in xAPIC mode */
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base.fields.xAPIC_enable = 1U;
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msr_write(MSR_IA32_APIC_BASE, base.value);
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/* Step2: Enable LAPIC in x2APIC mode */
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base.fields.x2APIC_enable = 1U;
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msr_write(MSR_IA32_APIC_BASE, base.value);
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}
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/**
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* @pre pcpu_id < 8U
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*/
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void init_lapic(uint16_t pcpu_id)
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{
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per_cpu(lapic_ldr, pcpu_id) = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LDR);
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/* Set the mask bits for all the LVT entries by disabling a local APIC software. */
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msr_write(MSR_IA32_EXT_APIC_SIVR, 0UL);
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/* Enable Local APIC */
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/* TODO: add spurious-interrupt handler */
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msr_write(MSR_IA32_EXT_APIC_SIVR, APIC_SVR_ENABLE | APIC_SVR_VECTOR);
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/* Ensure there are no ISR bits set. */
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clear_lapic_isr();
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}
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void save_lapic(struct lapic_regs *regs)
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{
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regs->tpr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TPR);
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regs->ppr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_PPR);
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regs->tmr[0].v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TMR0);
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regs->tmr[1].v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TMR1);
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regs->tmr[2].v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TMR2);
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regs->tmr[3].v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TMR3);
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regs->tmr[4].v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TMR4);
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regs->tmr[5].v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TMR5);
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regs->tmr[6].v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TMR6);
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regs->tmr[7].v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TMR7);
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regs->svr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_SIVR);
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regs->lvt[APIC_LVT_TIMER].v =
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(uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_TIMER);
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regs->lvt[APIC_LVT_LINT0].v =
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(uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_LINT0);
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regs->lvt[APIC_LVT_LINT1].v =
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(uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_LINT1);
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regs->lvt[APIC_LVT_ERROR].v =
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(uint32_t) msr_read(MSR_IA32_EXT_APIC_LVT_ERROR);
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regs->icr_timer.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_INIT_COUNT);
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regs->ccr_timer.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_CUR_COUNT);
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regs->dcr_timer.v =
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(uint32_t) msr_read(MSR_IA32_EXT_APIC_DIV_CONF);
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}
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static void restore_lapic(const struct lapic_regs *regs)
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{
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msr_write(MSR_IA32_EXT_APIC_TPR, (uint64_t) regs->tpr.v);
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msr_write(MSR_IA32_EXT_APIC_SIVR, (uint64_t) regs->svr.v);
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msr_write(MSR_IA32_EXT_APIC_LVT_TIMER,
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(uint64_t) regs->lvt[APIC_LVT_TIMER].v);
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msr_write(MSR_IA32_EXT_APIC_LVT_LINT0,
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(uint64_t) regs->lvt[APIC_LVT_LINT0].v);
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msr_write(MSR_IA32_EXT_APIC_LVT_LINT1,
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(uint64_t) regs->lvt[APIC_LVT_LINT1].v);
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msr_write(MSR_IA32_EXT_APIC_LVT_ERROR,
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(uint64_t) regs->lvt[APIC_LVT_ERROR].v);
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msr_write(MSR_IA32_EXT_APIC_INIT_COUNT, (uint64_t) regs->icr_timer.v);
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msr_write(MSR_IA32_EXT_APIC_DIV_CONF, (uint64_t) regs->dcr_timer.v);
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}
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void suspend_lapic(void)
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{
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uint64_t val;
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saved_lapic_base_msr.value = msr_read(MSR_IA32_APIC_BASE);
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save_lapic(&saved_lapic_regs);
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/* disable APIC with software flag */
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val = msr_read(MSR_IA32_EXT_APIC_SIVR);
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val = (~(uint64_t)APIC_SVR_ENABLE) & val;
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msr_write(MSR_IA32_EXT_APIC_SIVR, val);
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}
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void resume_lapic(void)
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{
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msr_write(MSR_IA32_APIC_BASE, saved_lapic_base_msr.value);
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/* ACPI software flag will be restored also */
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restore_lapic(&saved_lapic_regs);
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}
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void send_lapic_eoi(void)
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{
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msr_write(MSR_IA32_EXT_APIC_EOI, 0U);
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}
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uint32_t get_cur_lapic_id(void)
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{
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uint32_t lapic_id;
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lapic_id = (uint32_t) msr_read(MSR_IA32_EXT_XAPICID);
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return lapic_id;
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}
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void
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send_startup_ipi(uint16_t dest_pcpu_id, uint64_t cpu_startup_start_address)
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{
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union apic_icr icr;
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struct cpuinfo_x86 *cpu_info = get_pcpu_info();
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icr.value = 0U;
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icr.value_32.hi_32 = per_cpu(lapic_id, dest_pcpu_id);
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/* Assert INIT IPI */
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icr.bits.destination_mode = INTR_LAPIC_ICR_PHYSICAL;
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icr.bits.shorthand = INTR_LAPIC_ICR_USE_DEST_ARRAY;
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icr.bits.delivery_mode = INTR_LAPIC_ICR_INIT;
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msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
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/* Give 10ms for INIT sequence to complete for old processors.
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* BWG states that a delay cannot be avoided between the INIT IPI
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* and first Startup IPI, so on Modern processors (family == 6)
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* setting a delay value of 10us.
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*/
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if (cpu_info->family != 6U) {
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/* delay 10ms */
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udelay(10000U);
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} else {
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udelay(10U); /* 10us is enough for Modern processors */
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}
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/* Send Start IPI with page number of secondary reset code */
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icr.value_32.lo_32 = 0U;
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icr.bits.shorthand = INTR_LAPIC_ICR_USE_DEST_ARRAY;
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icr.bits.delivery_mode = INTR_LAPIC_ICR_STARTUP;
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icr.bits.vector = (uint8_t)(cpu_startup_start_address >> 12U);
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msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
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if (cpu_info->family == 6U) {
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udelay(10U); /* 10us is enough for Modern processors */
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} else {
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udelay(200U); /* 200us for old processors */
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}
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/* Send another start IPI as per the Intel Arch specification */
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msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
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}
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void send_dest_ipi_mask(uint32_t dest_mask, uint32_t vector)
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{
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uint16_t pcpu_id;
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uint32_t mask = dest_mask;
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pcpu_id = ffs64(mask);
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while (pcpu_id < MAX_PCPU_NUM) {
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bitmap32_clear_nolock(pcpu_id, &mask);
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send_single_ipi(pcpu_id, vector);
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pcpu_id = ffs64(mask);
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}
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}
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void send_single_ipi(uint16_t pcpu_id, uint32_t vector)
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{
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union apic_icr icr;
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if (is_pcpu_active(pcpu_id)) {
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if (get_pcpu_id() == pcpu_id) {
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msr_write(MSR_IA32_EXT_APIC_SELF_IPI, vector);
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} else {
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/* Set the destination field to the target processor. */
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icr.value_32.hi_32 = per_cpu(lapic_id, pcpu_id);
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/* Write the vector ID to ICR. */
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icr.value_32.lo_32 = vector | (INTR_LAPIC_ICR_PHYSICAL << 11U);
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msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
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}
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} else {
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pr_err("pcpu_id %d not in active!", pcpu_id);
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}
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}
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/**
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* @pre pcpu_id < MAX_PCPU_NUM
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*
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* @return None
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*/
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void send_single_nmi(uint16_t pcpu_id)
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{
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union apic_icr icr;
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icr.value_32.hi_32 = per_cpu(lapic_id, pcpu_id);
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icr.value_32.lo_32 = (INTR_LAPIC_ICR_PHYSICAL << 11U) | (INTR_LAPIC_ICR_NMI << 8U);
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msr_write(MSR_IA32_EXT_APIC_ICR, icr.value);
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}
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