505 lines
15 KiB
C
505 lines
15 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* this file contains vmcs operations which is vcpu related
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*/
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#include <types.h>
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#include <errno.h>
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#include <bits.h>
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#include <irq.h>
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#include <mmu.h>
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#include <vcpu.h>
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#include <vm.h>
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#include <vmx.h>
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#include <vtd.h>
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#include <vmexit.h>
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#include <pgtable.h>
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#include <cpufeatures.h>
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#include <trace.h>
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#include <logmsg.h>
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/* CR0 bits hv want to trap to track status change */
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#define CR0_TRAP_MASK (CR0_PE | CR0_PG | CR0_WP | CR0_CD | CR0_NW)
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#define CR0_RESERVED_MASK ~(CR0_PG | CR0_CD | CR0_NW | CR0_AM | CR0_WP | \
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CR0_NE | CR0_ET | CR0_TS | CR0_EM | CR0_MP | CR0_PE)
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/* CR4 bits hv want to trap to track status change */
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#define CR4_TRAP_MASK (CR4_PSE | CR4_PAE | CR4_VMXE | CR4_SMEP | CR4_SMAP | CR4_PKE | CR4_CET)
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#define CR4_RESERVED_MASK ~(CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | \
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CR4_PAE | CR4_MCE | CR4_PGE | CR4_PCE | \
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CR4_OSFXSR | CR4_PCIDE | CR4_OSXSAVE | \
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CR4_SMEP | CR4_FSGSBASE | CR4_VMXE | \
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CR4_OSXMMEXCPT | CR4_SMAP | CR4_PKE | \
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CR4_SMXE | CR4_UMIP | CR4_CET)
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/* PAE PDPTE bits 1 ~ 2, 5 ~ 8 are always reserved */
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#define PAE_PDPTE_FIXED_RESVD_BITS 0x00000000000001E6UL
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static uint64_t cr0_always_on_mask;
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static uint64_t cr0_always_off_mask;
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static uint64_t cr4_always_on_mask;
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static uint64_t cr4_always_off_mask;
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static int32_t load_pdptrs(const struct acrn_vcpu *vcpu)
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{
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uint64_t guest_cr3 = exec_vmread(VMX_GUEST_CR3);
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struct cpuinfo_x86 *cpu_info = get_pcpu_info();
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int32_t ret = 0;
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uint64_t pdpte[4]; /* Total four PDPTE */
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uint64_t rsvd_bits_mask;
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uint8_t maxphyaddr;
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int32_t i;
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/* check whether the address area pointed by the guest cr3
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* can be accessed or not
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*/
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if (copy_from_gpa(vcpu->vm, pdpte, get_pae_pdpt_addr(guest_cr3), sizeof(pdpte)) != 0) {
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ret = -EFAULT;
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} else {
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/* Check if any of the PDPTEs sets both the P flag
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* and any reserved bit
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*/
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maxphyaddr = cpu_info->phys_bits;
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/* reserved bits: 1~2, 5~8, maxphyaddr ~ 63 */
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rsvd_bits_mask = (63U < maxphyaddr) ? 0UL : (((1UL << (63U - maxphyaddr + 1U)) - 1UL) << maxphyaddr);
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rsvd_bits_mask |= PAE_PDPTE_FIXED_RESVD_BITS;
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for (i = 0; i < 4; i++) {
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if (((pdpte[i] & PAGE_PRESENT) != 0UL) && ((pdpte[i] & rsvd_bits_mask) != 0UL)) {
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ret = -EFAULT;
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break;
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}
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}
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}
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if (ret == 0) {
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exec_vmwrite64(VMX_GUEST_PDPTE0_FULL, pdpte[0]);
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exec_vmwrite64(VMX_GUEST_PDPTE1_FULL, pdpte[1]);
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exec_vmwrite64(VMX_GUEST_PDPTE2_FULL, pdpte[2]);
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exec_vmwrite64(VMX_GUEST_PDPTE3_FULL, pdpte[3]);
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}
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return ret;
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}
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static bool is_cr0_write_valid(struct acrn_vcpu *vcpu, uint64_t cr0)
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{
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bool ret = true;
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/* Shouldn't set always off bit */
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if ((cr0 & cr0_always_off_mask) != 0UL) {
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ret = false;
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} else {
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/* SDM 25.3 "Changes to instruction behavior in VMX non-root"
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*
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* We always require "unrestricted guest" control enabled. So
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*
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* CR0.PG = 1, CR4.PAE = 0 and IA32_EFER.LME = 1 is invalid.
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* CR0.PE = 0 and CR0.PG = 1 is invalid.
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*/
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if (((cr0 & CR0_PG) != 0UL) && (!is_pae(vcpu)) &&
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((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL)) {
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ret = false;
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} else {
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if (((cr0 & CR0_PE) == 0UL) && ((cr0 & CR0_PG) != 0UL)) {
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ret = false;
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} else {
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/* SDM 6.15 "Exception and Interrupt Refrerence" GP Exception
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*
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* Loading CR0 register with a set NW flag and a clear CD flag
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* is invalid
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*/
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if (((cr0 & CR0_CD) == 0UL) && ((cr0 & CR0_NW) != 0UL)) {
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ret = false;
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}
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/* SDM 4.10.1 "Process-Context Identifiers"
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*
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* MOV to CR0 causes a general-protection exception if it would
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* clear CR0.PG to 0 while CR4.PCIDE = 1
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*/
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if (((cr0 & CR0_PG) == 0UL) && ((vcpu_get_cr4(vcpu) & CR4_PCIDE) != 0UL)) {
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ret = false;
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}
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}
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}
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}
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return ret;
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}
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/*
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* Handling of CR0:
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* Assume "unrestricted guest" feature is supported by vmx.
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* For mode switch, hv only needs to take care of enabling/disabling long mode,
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* thanks to "unrestricted guest" feature.
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*
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* - PE (0) Trapped to track cpu mode.
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* Set the value according to the value from guest.
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* - MP (1) Flexible to guest
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* - EM (2) Flexible to guest
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* - TS (3) Flexible to guest
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* - ET (4) Flexible to guest
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* - NE (5) must always be 1
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* - WP (16) Trapped to get if it inhibits supervisor level procedures to
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* write into ro-pages.
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* - AM (18) Flexible to guest
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* - NW (29) Trapped to emulate cache disable situation
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* - CD (30) Trapped to emulate cache disable situation
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* - PG (31) Trapped to track cpu/paging mode.
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* Set the value according to the value from guest.
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*/
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static void vmx_write_cr0(struct acrn_vcpu *vcpu, uint64_t cr0)
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{
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bool err_found = false;
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if (!is_cr0_write_valid(vcpu, cr0)) {
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pr_dbg("Invalid cr0 write operation from guest");
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vcpu_inject_gp(vcpu, 0U);
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} else {
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uint64_t cr0_vmx;
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uint32_t entry_ctrls;
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bool old_paging_enabled = is_paging_enabled(vcpu);
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uint64_t cr0_changed_bits = vcpu_get_cr0(vcpu) ^ cr0;
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uint64_t cr0_mask = cr0;
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/* SDM 2.5
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* When loading a control register, reserved bit should always set
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* to the value previously read.
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*/
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cr0_mask &= ~CR0_RESERVED_MASK;
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if (!old_paging_enabled && ((cr0_mask & CR0_PG) != 0UL)) {
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if ((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL) {
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/* Enable long mode */
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pr_dbg("VMM: Enable long mode");
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entry_ctrls = exec_vmread32(VMX_ENTRY_CONTROLS);
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entry_ctrls |= VMX_ENTRY_CTLS_IA32E_MODE;
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exec_vmwrite32(VMX_ENTRY_CONTROLS, entry_ctrls);
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vcpu_set_efer(vcpu, vcpu_get_efer(vcpu) | MSR_IA32_EFER_LMA_BIT);
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} else if (is_pae(vcpu)) {
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/* enabled PAE from paging disabled */
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if (load_pdptrs(vcpu) != 0) {
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err_found = true;
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vcpu_inject_gp(vcpu, 0U);
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}
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} else {
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/* do nothing */
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}
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} else if (old_paging_enabled && ((cr0_mask & CR0_PG) == 0UL)) {
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if ((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL) {
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/* Disable long mode */
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pr_dbg("VMM: Disable long mode");
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entry_ctrls = exec_vmread32(VMX_ENTRY_CONTROLS);
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entry_ctrls &= ~VMX_ENTRY_CTLS_IA32E_MODE;
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exec_vmwrite32(VMX_ENTRY_CONTROLS, entry_ctrls);
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vcpu_set_efer(vcpu, vcpu_get_efer(vcpu) & ~MSR_IA32_EFER_LMA_BIT);
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}
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} else {
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/* do nothing */
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}
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if (err_found == false) {
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/* If CR0.CD or CR0.NW get cr0_changed_bits */
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if ((cr0_changed_bits & (CR0_CD | CR0_NW)) != 0UL) {
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/* No action if only CR0.NW is cr0_changed_bits */
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if ((cr0_changed_bits & CR0_CD) != 0UL) {
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if ((cr0_mask & CR0_CD) != 0UL) {
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/*
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* When the guest requests to set CR0.CD, we don't allow
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* guest's CR0.CD to be actually set, instead, we write guest
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* IA32_PAT with all-UC entries to emulate the cache
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* disabled behavior
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*/
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, PAT_ALL_UC_VALUE);
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cache_flush_invalidate_all();
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} else {
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/* Restore IA32_PAT to enable cache again */
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL,
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vcpu_get_guest_msr(vcpu, MSR_IA32_PAT));
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}
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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}
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if ((cr0_changed_bits & (CR0_PG | CR0_WP)) != 0UL) {
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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/* CR0 has no always off bits, except the always on bits, and reserved
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* bits, allow to set according to guest.
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*/
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cr0_vmx = cr0_always_on_mask | cr0_mask;
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/* Don't set CD or NW bit to guest */
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cr0_vmx &= ~(CR0_CD | CR0_NW);
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exec_vmwrite(VMX_GUEST_CR0, cr0_vmx & 0xFFFFFFFFUL);
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exec_vmwrite(VMX_CR0_READ_SHADOW, cr0_mask & 0xFFFFFFFFUL);
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/* clear read cache, next time read should from VMCS */
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bitmap_clear_lock(CPU_REG_CR0, &vcpu->reg_cached);
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pr_dbg("VMM: Try to write %016lx, allow to write 0x%016lx to CR0", cr0_mask, cr0_vmx);
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}
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}
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}
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static bool is_cr4_write_valid(struct acrn_vcpu *vcpu, uint64_t cr4)
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{
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bool ret = true;
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/* Check if guest try to set fixed to 0 bits or reserved bits */
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if ((cr4 & cr4_always_off_mask) != 0U) {
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ret = false;
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} else {
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/* Do NOT support nested guest, nor SMX */
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if (((cr4 & CR4_VMXE) != 0UL) || ((cr4 & CR4_SMXE) != 0UL) || ((cr4 & CR4_CET) != 0UL)) {
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ret = false;
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} else {
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if (is_long_mode(vcpu)) {
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if ((cr4 & CR4_PAE) == 0UL) {
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ret = false;
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}
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}
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}
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}
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return ret;
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}
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/*
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* Handling of CR4:
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* Assume "unrestricted guest" feature is supported by vmx.
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*
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* For CR4, if some feature is not supported by hardware, the corresponding bit
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* will be set in cr4_always_off_mask. If guest try to set these bits after
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* vmexit, will inject a #GP.
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* If a bit for a feature not supported by hardware, which is flexible to guest,
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* and write to it do not lead to a VM exit, a #GP should be generated inside
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* guest.
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*
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* - VME (0) Flexible to guest
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* - PVI (1) Flexible to guest
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* - TSD (2) Flexible to guest
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* - DE (3) Flexible to guest
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* - PSE (4) Trapped to track paging mode.
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* Set the value according to the value from guest.
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* - PAE (5) Trapped to track paging mode.
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* Set the value according to the value from guest.
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* - MCE (6) Trapped to hide from guest
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* - PGE (7) Flexible to guest
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* - PCE (8) Flexible to guest
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* - OSFXSR (9) Flexible to guest
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* - OSXMMEXCPT (10) Flexible to guest
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* - VMXE (13) Trapped to hide from guest
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* - SMXE (14) must always be 0 => must lead to a VM exit
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* - PCIDE (17) Flexible tol guest
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* - OSXSAVE (18) Flexible to guest
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* - XSAVE (19) Flexible to guest
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* We always keep align with physical cpu. So it's flexible to
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* guest
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* - SMEP (20) Flexible to guest
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* - SMAP (21) Flexible to guest
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* - PKE (22) Flexible to guest
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* - CET (23) Trapped to hide from guest
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*/
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static void vmx_write_cr4(struct acrn_vcpu *vcpu, uint64_t cr4)
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{
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bool err_found = false;
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if (!is_cr4_write_valid(vcpu, cr4)) {
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pr_dbg("Invalid cr4 write operation from guest");
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vcpu_inject_gp(vcpu, 0U);
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} else {
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uint64_t cr4_vmx, cr4_shadow;
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uint64_t old_cr4 = vcpu_get_cr4(vcpu);
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if (((cr4 ^ old_cr4) & (CR4_PGE | CR4_PSE | CR4_PAE | CR4_SMEP | CR4_SMAP | CR4_PKE)) != 0UL) {
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if (((cr4 & CR4_PAE) != 0UL) && (is_paging_enabled(vcpu)) && (!is_long_mode(vcpu))) {
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if (load_pdptrs(vcpu) != 0) {
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err_found = true;
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vcpu_inject_gp(vcpu, 0U);
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}
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}
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if (err_found == false) {
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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}
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if ((err_found == false) && (((cr4 ^ old_cr4) & CR4_PCIDE) != 0UL)) {
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/* MOV to CR4 causes a general-protection exception (#GP) if it would change
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* CR4.PCIDE from 0 to 1 and either IA32_EFER.LMA = 0 or CR3[11:0] != 000H
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*/
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if ((cr4 & CR4_PCIDE) != 0UL) {
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uint64_t guest_cr3 = exec_vmread(VMX_GUEST_CR3);
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/* For now, HV passes-through PCID capability to guest, check X86_FEATURE_PCID of
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* pcpu capabilities directly.
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*/
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if ((!pcpu_has_cap(X86_FEATURE_PCID)) || (!is_long_mode(vcpu)) ||
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((guest_cr3 & 0xFFFUL) != 0UL)) {
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pr_dbg("Failed to enable CR4.PCIE");
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err_found = true;
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vcpu_inject_gp(vcpu, 0U);
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}
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} else {
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/* The instruction invalidates all TLB entries (including global entries) and
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* all entries in all paging-structure caches (for all PCIDs) if it changes the
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* value of the CR4.PCIDE from 1 to 0
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*/
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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}
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if (err_found == false) {
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/* Clear forced off bits */
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cr4_shadow = cr4 & ~CR4_MCE;
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cr4_vmx = cr4_always_on_mask | cr4_shadow;
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exec_vmwrite(VMX_GUEST_CR4, cr4_vmx & 0xFFFFFFFFUL);
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exec_vmwrite(VMX_CR4_READ_SHADOW, cr4_shadow & 0xFFFFFFFFUL);
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/* clear read cache, next time read should from VMCS */
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bitmap_clear_lock(CPU_REG_CR4, &vcpu->reg_cached);
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pr_dbg("VMM: Try to write %016lx, allow to write 0x%016lx to CR4", cr4, cr4_vmx);
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}
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}
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}
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void init_cr0_cr4_host_mask(void)
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{
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static bool inited = false;
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static uint64_t cr0_host_owned_bits, cr4_host_owned_bits;
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uint64_t fixed0, fixed1;
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if (!inited) {
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/* Read the CR0 fixed0 / fixed1 MSR registers */
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fixed0 = msr_read(MSR_IA32_VMX_CR0_FIXED0);
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fixed1 = msr_read(MSR_IA32_VMX_CR0_FIXED1);
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cr0_host_owned_bits = ~(fixed0 ^ fixed1);
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/* Add the bit hv wants to trap */
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cr0_host_owned_bits |= CR0_TRAP_MASK;
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cr0_host_owned_bits &= ~CR0_RESERVED_MASK;
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/* CR0 clear PE/PG from always on bits due to "unrestructed guest" feature */
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cr0_always_on_mask = fixed0 & (~(CR0_PE | CR0_PG));
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cr0_always_off_mask = ~fixed1;
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/* SDM 2.5
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* bit 63:32 of CR0 and CR4 ar reserved and must be written
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* zero. We could merge it with always off mask.
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*/
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cr0_always_off_mask |= 0xFFFFFFFF00000000UL;
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/* Read the CR4 fixed0 / fixed1 MSR registers */
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fixed0 = msr_read(MSR_IA32_VMX_CR4_FIXED0);
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fixed1 = msr_read(MSR_IA32_VMX_CR4_FIXED1);
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cr4_host_owned_bits = ~(fixed0 ^ fixed1);
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/* Add the bit hv wants to trap */
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cr4_host_owned_bits |= CR4_TRAP_MASK;
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cr4_host_owned_bits &= ~CR4_RESERVED_MASK;
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cr4_always_on_mask = fixed0;
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/* Record the bit fixed to 0 for CR4, including reserved bits */
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cr4_always_off_mask = ~fixed1;
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/* SDM 2.5
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* bit 63:32 of CR0 and CR4 ar reserved and must be written
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* zero. We could merge it with always off mask.
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*/
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cr4_always_off_mask |= 0xFFFFFFFF00000000UL;
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cr4_always_off_mask |= CR4_RESERVED_MASK;
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inited = true;
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}
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exec_vmwrite(VMX_CR0_GUEST_HOST_MASK, cr0_host_owned_bits);
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/* Output CR0 mask value */
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pr_dbg("CR0 guest-host mask value: 0x%016lx", cr0_host_owned_bits);
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exec_vmwrite(VMX_CR4_GUEST_HOST_MASK, cr4_host_owned_bits);
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/* Output CR4 mask value */
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pr_dbg("CR4 guest-host mask value: 0x%016lx", cr4_host_owned_bits);
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}
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uint64_t vcpu_get_cr0(struct acrn_vcpu *vcpu)
|
|
{
|
|
uint64_t mask;
|
|
struct run_context *ctx = &vcpu->arch.contexts[vcpu->arch.cur_context].run_ctx;
|
|
|
|
if (bitmap_test_and_set_lock(CPU_REG_CR0, &vcpu->reg_cached) == 0) {
|
|
mask = exec_vmread(VMX_CR0_GUEST_HOST_MASK);
|
|
ctx->cr0 = (exec_vmread(VMX_CR0_READ_SHADOW) & mask) |
|
|
(exec_vmread(VMX_GUEST_CR0) & (~mask));
|
|
}
|
|
return ctx->cr0;
|
|
}
|
|
|
|
void vcpu_set_cr0(struct acrn_vcpu *vcpu, uint64_t val)
|
|
{
|
|
vmx_write_cr0(vcpu, val);
|
|
}
|
|
|
|
uint64_t vcpu_get_cr2(const struct acrn_vcpu *vcpu)
|
|
{
|
|
return vcpu->arch.contexts[vcpu->arch.cur_context].run_ctx.cr2;
|
|
}
|
|
|
|
void vcpu_set_cr2(struct acrn_vcpu *vcpu, uint64_t val)
|
|
{
|
|
vcpu->arch.contexts[vcpu->arch.cur_context].run_ctx.cr2 = val;
|
|
}
|
|
|
|
uint64_t vcpu_get_cr4(struct acrn_vcpu *vcpu)
|
|
{
|
|
uint64_t mask;
|
|
struct run_context *ctx = &vcpu->arch.contexts[vcpu->arch.cur_context].run_ctx;
|
|
|
|
if (bitmap_test_and_set_lock(CPU_REG_CR4, &vcpu->reg_cached) == 0) {
|
|
mask = exec_vmread(VMX_CR4_GUEST_HOST_MASK);
|
|
ctx->cr4 = (exec_vmread(VMX_CR4_READ_SHADOW) & mask) |
|
|
(exec_vmread(VMX_GUEST_CR4) & (~mask));
|
|
}
|
|
return ctx->cr4;
|
|
}
|
|
|
|
void vcpu_set_cr4(struct acrn_vcpu *vcpu, uint64_t val)
|
|
{
|
|
vmx_write_cr4(vcpu, val);
|
|
}
|
|
|
|
int32_t cr_access_vmexit_handler(struct acrn_vcpu *vcpu)
|
|
{
|
|
uint64_t reg;
|
|
uint32_t idx;
|
|
uint64_t exit_qual;
|
|
int32_t ret = 0;
|
|
|
|
exit_qual = vcpu->arch.exit_qualification;
|
|
idx = (uint32_t)vm_exit_cr_access_reg_idx(exit_qual);
|
|
|
|
ASSERT((idx <= 15U), "index out of range");
|
|
reg = vcpu_get_gpreg(vcpu, idx);
|
|
|
|
switch ((vm_exit_cr_access_type(exit_qual) << 4U) | vm_exit_cr_access_cr_num(exit_qual)) {
|
|
case 0x00UL:
|
|
/* mov to cr0 */
|
|
vcpu_set_cr0(vcpu, reg);
|
|
break;
|
|
case 0x04UL:
|
|
/* mov to cr4 */
|
|
vcpu_set_cr4(vcpu, reg);
|
|
break;
|
|
default:
|
|
ASSERT(false, "Unhandled CR access");
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
TRACE_2L(TRACE_VMEXIT_CR_ACCESS, vm_exit_cr_access_type(exit_qual),
|
|
vm_exit_cr_access_cr_num(exit_qual));
|
|
|
|
return ret;
|
|
}
|