131 lines
5.2 KiB
C
131 lines
5.2 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef UART16550_H
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#define UART16550_H
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/* Register / bit definitions for 16c550 uart */
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#define UART16550_RBR 0x00
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/*receive buffer register | base+00h, dlab=0b r*/
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#define UART16550_THR 0x00
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/*transmit holding register | base+00h, dlab=0b w*/
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#define UART16550_DLL 0x00
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/*divisor least significant byte | base+00h, dlab=1b rw*/
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#define UART16550_IER 0x01
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/*interrupt enable register | base+01h, dlab=0b rw*/
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#define UART16550_DLM 0x01
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/*divisor most significant byte | base+01h, dlab=1b rw*/
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#define UART16550_IIR 0x02
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/*interrupt identification register | base+02h, dlab=0b r*/
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#define UART16550_FCR 0x02
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/*fifo control register | base+02h, dlab=0b w*/
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#define UART16550_LCR 0x03
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/*line control register | base+03h, dlab=xb rw*/
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#define UART16550_MCR 0x04
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/*modem control register, only uart0 | base+04h, dlab=xb rw*/
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#define UART16550_LSR 0x05
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/*line status register | base+05h, dlab=xb r*/
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#define UART16550_MSR 0x06
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/*modem status register, only uart0 | base+06h, dlab=xb r*/
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#define UART16550_SCR 0x07
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/*scratch pad register | base+07h, dlab=xb rw*/
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#define UART16550_MDR1 0x08
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#define UARTML7213_BRCSR 0x0e
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/*baud rate reference clock select register dlab xb*/
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#define UARTML7213_SRST 0x0f /*Soft Reset Register dlab xb*/
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/* value definitions for IIR */
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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#define IIR_RXTOUT 0x0c
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#define IIR_RLS 0x06
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#define IIR_RXRDY 0x04
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#define IIR_TXRDY 0x02
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#define IIR_NOPEND 0x01
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#define IIR_MLSC 0x00
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#define IER_EDSSI (0x0008)
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/*enable/disable modem status interrupt*/
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#define IER_ELSI (0x0004)
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/*enable/disable receive data error interrupt*/
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#define IER_ETBEI (0x0002)
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/*enable/disable transmit data write request interrupt*/
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#define IER_ERBFI (0x0001)
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/*enable/disable receive data read request interrupt*/
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/* definition for LCR */
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#define LCR_DLAB (1 << 7) /*DLAB THR/RBR&IER or DLL&DLM= Bit 7*/
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#define LCR_SB (1 << 6) /*break control on/off= Bit 6*/
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#define LCR_SP (1 << 5) /*Specifies the operation of parity bit*/
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#define LCR_EPS (1 << 4) /*Specifies the logic of a parity bit*/
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#define LCR_PEN (1 << 3) /*Specifies whether to add a parity bit*/
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#define LCR_STB (1 << 2) /*stop bit length*/
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#define LCR_WL8 (0x03) /*number of bits of serial data*/
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#define LCR_WL7 (0x02) /*number of bits of serial data*/
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#define LCR_WL6 (0x01) /*number of bits of serial data*/
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#define LCR_WL5 (0x00) /*number of bits of serial data*/
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#define LCR_PARITY_ODD (LCR_PEN)
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#define LCR_PARITY_NONE 0x0
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#define LCR_PARITY_EVEN (LCR_PEN | LCR_EPS)
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#define LCR_NB_STOP_BITS_1 0x0
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#define LCR_NB_STOP_BITS_2 (LCR_STB)
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/* bit definitions for LSR */
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/* at least one error in data within fifo */
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#define LSR_ERR (1 << 7)
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/* Transmit data Present */
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#define LSR_TEMT (1 << 6)
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/* Transmit data write request present */
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#define LSR_THRE (1 << 5)
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/* Break interrupt data Present */
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#define LSR_BI (1 << 4)
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/* Framing Error Occurred */
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#define LSR_FE (1 << 3)
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/* Parity Error Occurred */
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#define LSR_PE (1 << 2)
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/* Overrun error */
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#define LSR_OE (1 << 1)
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/* Readable received data is present */
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#define LSR_DR (1 << 0)
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/* definition for MCR */
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#define MCR_RTS (1 << 1) /* Request to Send */
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#define MCR_DTR (1 << 0) /* Data Terminal Ready */
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/* definition for FCR */
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#define FCR_RX_MASK 0xc0
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#define FCR_DMA (1 << 3)
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#define FCR_TFR (1 << 2) /* Reset Transmit Fifo */
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#define FCR_RFR (1 << 1) /* Reset Receive Fifo */
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#define FCR_FIFOE (1 << 0) /* Fifo Enable */
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#define UART_IER_DISABLE_ALL 0x00000000
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#endif /* !UART16550_H */
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