217 lines
6.5 KiB
C
217 lines
6.5 KiB
C
/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <asm/guest/vm.h>
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#include "vpci_priv.h"
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#include <asm/guest/ept.h>
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#include <asm/guest/virq.h>
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#include <logmsg.h>
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#include <hash.h>
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/**
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* @pre vdev != NULL
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*/
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uint32_t pci_vdev_read_vcfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes)
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{
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uint32_t val;
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switch (bytes) {
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case 1U:
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val = vdev->cfgdata.data_8[offset];
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break;
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case 2U:
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val = vdev->cfgdata.data_16[offset >> 1U];
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break;
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default:
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val = vdev->cfgdata.data_32[offset >> 2U];
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break;
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}
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return val;
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}
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/**
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* @pre vdev != NULL
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*/
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void pci_vdev_write_vcfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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switch (bytes) {
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case 1U:
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vdev->cfgdata.data_8[offset] = (uint8_t)val;
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break;
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case 2U:
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vdev->cfgdata.data_16[offset >> 1U] = (uint16_t)val;
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break;
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default:
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vdev->cfgdata.data_32[offset >> 2U] = val;
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break;
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}
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}
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/**
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* @pre vpci != NULL
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* @pre vpci->pci_vdev_cnt <= CONFIG_MAX_PCI_DEV_NUM
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*/
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struct pci_vdev *pci_find_vdev(struct acrn_vpci *vpci, union pci_bdf vbdf)
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{
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struct pci_vdev *vdev = NULL, *tmp;
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struct hlist_node *n;
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hlist_for_each(n, &vpci->vdevs_hlist_heads[hash64(vbdf.value, VDEV_LIST_HASHBITS)]) {
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tmp = hlist_entry(n, struct pci_vdev, link);
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if (bdf_is_equal(vbdf, tmp->bdf)) {
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vdev = tmp;
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break;
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}
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}
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return vdev;
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}
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static bool is_pci_mem_bar_base_valid(struct acrn_vm *vm, uint64_t base)
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{
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struct acrn_vpci *vpci = &vm->vpci;
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struct pci_mmio_res *res = (base < (1UL << 32UL)) ? &(vpci->res32): &(vpci->res64);
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return ((base >= res->start) && (base <= res->end));
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}
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static void pci_vdev_update_vbar_base(struct pci_vdev *vdev, uint32_t idx)
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{
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struct pci_vbar *vbar;
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uint64_t base = 0UL;
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uint32_t lo, hi, offset;
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struct pci_mmio_res *res;
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vbar = &vdev->vbars[idx];
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offset = pci_bar_offset(idx);
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lo = pci_vdev_read_vcfg(vdev, offset, 4U);
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if ((!is_pci_reserved_bar(vbar)) && (lo != (vbar->mask | vbar->bar_type.bits))) {
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base = lo & vbar->mask;
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if (is_pci_mem64lo_bar(vbar)) {
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vbar = &vdev->vbars[idx + 1U];
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hi = pci_vdev_read_vcfg(vdev, (offset + 4U), 4U);
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if (hi != vbar->mask) {
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base |= ((uint64_t)hi << 32U);
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} else {
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base = 0UL;
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}
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}
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if (is_pci_io_bar(vbar)) {
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/* Because guest driver may write to upper 16-bits of PIO BAR and expect that should have no effect,
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* SO PIO BAR base may bigger than 0xffff after calculation, should mask the upper 16-bits.
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*/
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base &= 0xffffUL;
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}
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}
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if (base != 0UL) {
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if (is_pci_io_bar(vbar)) {
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/*
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* ACRN-DM and acrn-config should ensure the identical mapping of PIO bar of pass-thru devs.
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* Currently, we don't support the reprogram of PIO bar of pass-thru devs,
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* If guest tries to reprogram, hv will inject #GP to guest.
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*/
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if ((vdev->pdev != NULL) && ((lo & PCI_BASE_ADDRESS_IO_MASK) != (uint32_t)vbar->base_hpa)) {
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struct acrn_vcpu *vcpu = vcpu_from_pid(vpci2vm(vdev->vpci), get_pcpu_id());
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if (vcpu != NULL) {
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vcpu_inject_gp(vcpu, 0U);
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}
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pr_err("%s, PCI:%02x:%02x.%x PIO BAR%d couldn't be reprogramed, "
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"the valid value is 0x%lx, but the actual value is 0x%lx",
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__func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx,
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vdev->vbars[idx].base_hpa, lo & PCI_BASE_ADDRESS_IO_MASK);
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base = 0UL;
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}
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} else {
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if ((!is_pci_mem_bar_base_valid(vpci2vm(vdev->vpci), base))
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|| (!mem_aligned_check(base, vdev->vbars[idx].size))) {
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res = (base < (1UL << 32UL)) ? &(vdev->vpci->res32) : &(vdev->vpci->res64);
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/* VM tries to reprogram vbar address out of pci mmio bar window, it can be caused by:
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* 1. For Service VM, <board>.xml is misaligned with the actual native platform,
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* and we get wrong mmio window.
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* 2. Malicious operation from VM, it tries to reprogram vbar address out of
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* pci mmio bar window
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*/
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pr_err("%s reprogram PCI:%02x:%02x.%x BAR%d to addr:0x%lx,"
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" which is out of mmio window[0x%lx - 0x%lx] or not aligned with size: 0x%lx",
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__func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx, base,
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res->start, res->end, vdev->vbars[idx].size);
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}
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}
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}
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vdev->vbars[idx].base_gpa = base;
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}
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int32_t check_pt_dev_pio_bars(struct pci_vdev *vdev)
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{
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int32_t ret = 0;
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uint32_t idx;
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if (vdev->pdev != NULL) {
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for (idx = 0U; idx < vdev->nr_bars; idx++) {
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if ((is_pci_io_bar(&vdev->vbars[idx])) && (vdev->vbars[idx].base_gpa != vdev->vbars[idx].base_hpa)) {
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ret = -EIO;
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pr_err("%s, PCI:%02x:%02x.%x PIO BAR%d isn't identical mapping, "
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"host start addr is 0x%lx, while guest start addr is 0x%lx",
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__func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx,
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vdev->vbars[idx].base_hpa, vdev->vbars[idx].base_gpa);
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break;
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}
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}
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}
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return ret;
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}
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void pci_vdev_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val)
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{
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struct pci_vbar *vbar;
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uint32_t bar, offset;
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uint32_t update_idx = idx;
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vbar = &vdev->vbars[idx];
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bar = val & vbar->mask;
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if (vbar->is_mem64hi) {
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update_idx -= 1U;
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} else {
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if (is_pci_io_bar(vbar)) {
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bar |= (vbar->bar_type.bits & (~PCI_BASE_ADDRESS_IO_MASK));
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} else {
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bar |= (vbar->bar_type.bits & (~PCI_BASE_ADDRESS_MEM_MASK));
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}
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}
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offset = pci_bar_offset(idx);
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pci_vdev_write_vcfg(vdev, offset, 4U, bar);
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pci_vdev_update_vbar_base(vdev, update_idx);
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}
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