129 lines
3.6 KiB
C
129 lines
3.6 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <asm/mmu.h>
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#include <asm/per_cpu.h>
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#include <asm/trampoline.h>
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#include <reloc.h>
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#include <asm/boot/ld_sym.h>
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#include <asm/e820.h>
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static uint64_t trampoline_start16_paddr;
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/*
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* Because trampoline code is relocated in different way, if HV code
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* accesses trampoline using relative addressing, it needs to take
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* out the HV relocation delta
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*
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* This function is valid if:
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* - The hpa of HV code is always higher than trampoline code
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* - The HV code is always relocated to higher address, compared
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* with CONFIG_HV_RAM_START
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*/
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static uint64_t trampoline_relo_addr(const void *addr)
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{
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return (uint64_t)addr - get_hv_image_delta();
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}
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uint64_t read_trampoline_sym(const void *sym)
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{
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uint64_t *hva = (uint64_t *)(hpa2hva(trampoline_start16_paddr) + trampoline_relo_addr(sym));
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return *hva;
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}
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void write_trampoline_sym(const void *sym, uint64_t val)
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{
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uint64_t *hva = (uint64_t *)(hpa2hva(trampoline_start16_paddr) + trampoline_relo_addr(sym));
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*hva = val;
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clflush(hva);
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}
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void write_trampoline_stack_sym(uint16_t pcpu_id)
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{
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uint64_t *hva, stack_sym_addr;
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hva = (uint64_t *)(hpa2hva(trampoline_start16_paddr) + trampoline_relo_addr(secondary_cpu_stack));
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stack_sym_addr = (uint64_t)&per_cpu(stack, pcpu_id)[CONFIG_STACK_SIZE - 1];
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stack_sym_addr &= ~(CPU_STACK_ALIGN - 1UL);
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*hva = stack_sym_addr;
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clflush(hva);
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}
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uint64_t get_trampoline_start16_paddr(void)
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{
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return trampoline_start16_paddr;
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}
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static void update_trampoline_code_refs(uint64_t dest_pa)
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{
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void *ptr;
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uint64_t val;
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uint32_t i;
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/*
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* calculate the fixup CS:IP according to fixup target address
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* dynamically.
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*
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* trampoline code starts in real mode,
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* so the target addres is HPA
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*/
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val = dest_pa + trampoline_relo_addr(&trampoline_fixup_target);
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_fixup_cs));
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*(uint16_t *)(ptr) = (uint16_t)((val >> 4U) & 0xFFFFU);
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_fixup_ip));
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*(uint16_t *)(ptr) = (uint16_t)(val & 0xfU);
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/* Update temporary page tables */
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&cpu_boot_page_tables_ptr));
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*(uint32_t *)(ptr) += (uint32_t)dest_pa;
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&cpu_boot_page_tables_start));
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*(uint64_t *)(ptr) += dest_pa;
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_pdpt_addr));
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for (i = 0U; i < 4U; i++) {
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*(uint64_t *)(ptr + sizeof(uint64_t) * i) += dest_pa;
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}
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/* update the gdt base pointer with relocated offset */
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_gdt_ptr));
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*(uint64_t *)(ptr + 2) += dest_pa;
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/* update trampoline jump pointer with relocated offset */
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_start64_fixup));
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*(uint32_t *)ptr += (uint32_t)dest_pa;
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/* update trampoline's main entry pointer */
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ptr = hpa2hva(dest_pa + trampoline_relo_addr(main_entry));
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*(uint64_t *)ptr += get_hv_image_delta();
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}
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uint64_t prepare_trampoline(void)
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{
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uint64_t trampline_size, trampoline_pa;
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trampline_size = (uint64_t)(&ld_trampoline_end - &ld_trampoline_start);
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trampoline_pa = e820_alloc_memory(trampline_size, MEM_1M);
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pr_dbg("trampoline code: %lx trampline_size %x", trampoline_pa, trampline_size);
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/* Copy segment for AP initialization code below 1MB */
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(void)memcpy_s(hpa2hva(trampoline_pa), (size_t)trampline_size, &ld_trampoline_load,
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(size_t)trampline_size);
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update_trampoline_code_refs(trampoline_pa);
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cpu_memory_barrier();
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flush_cache_range(hpa2hva(trampoline_pa), trampline_size);
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trampoline_start16_paddr = trampoline_pa;
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return trampoline_pa;
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}
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