222 lines
7.4 KiB
C
222 lines
7.4 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef VPCI_H_
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#define VPCI_H_
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#include <asm/lib/spinlock.h>
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#include <pci.h>
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#include <list.h>
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#define VDEV_LIST_HASHBITS 4U
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#define VDEV_LIST_HASHSIZE (1U << VDEV_LIST_HASHBITS)
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struct pci_vbar {
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bool is_mem64hi; /* this is to indicate the high part of 64 bits MMIO bar */
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uint64_t size; /* BAR size */
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uint64_t base_gpa; /* BAR guest physical address */
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uint64_t base_hpa; /* BAR host physical address */
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union pci_bar_type bar_type; /* the low 2(PIO)/4(MMIO) bits of BAR */
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uint32_t mask; /* BAR size mask */
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};
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struct msix_table_entry {
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uint64_t addr;
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uint32_t data;
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uint32_t vector_control;
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};
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/* MSI capability structure */
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struct pci_msi {
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bool is_64bit;
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uint32_t capoff;
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uint32_t caplen;
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};
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/* MSI-X capability structure */
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struct msixcap {
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uint8_t capid;
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uint8_t nextptr;
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uint16_t msgctrl;
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uint32_t table_info; /* bar index and offset */
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uint32_t pba_info; /* bar index and offset */
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} __packed;
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struct pci_msix {
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struct msix_table_entry table_entries[CONFIG_MAX_MSIX_TABLE_NUM];
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uint64_t mmio_gpa;
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uint64_t mmio_hpa;
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uint64_t mmio_size;
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uint32_t capoff;
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uint32_t caplen;
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uint32_t table_bar;
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uint32_t table_offset;
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uint32_t table_count;
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bool is_vmsix_on_msi;
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bool is_vmsix_on_msi_programmed;
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};
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/* SRIOV capability structure */
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struct pci_cap_sriov {
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uint32_t capoff;
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uint32_t caplen;
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/*
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* If the vdev is a SRIOV PF vdev, the vbars is used to store
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* the bar information that is using to initialize SRIOV VF vdev bar.
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*/
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struct pci_vbar vbars[PCI_BAR_COUNT];
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};
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union pci_cfgdata {
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uint8_t data_8[PCIE_CONFIG_SPACE_SIZE];
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uint16_t data_16[PCIE_CONFIG_SPACE_SIZE >> 1U];
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uint32_t data_32[PCIE_CONFIG_SPACE_SIZE >> 2U];
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};
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struct pci_vdev;
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struct pci_vdev_ops {
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void (*init_vdev)(struct pci_vdev *vdev);
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void (*deinit_vdev)(struct pci_vdev *vdev);
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int32_t (*write_vdev_cfg)(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val);
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int32_t (*read_vdev_cfg)(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t *val);
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};
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struct pci_vdev {
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struct acrn_vpci *vpci;
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/* The bus/device/function triple of the virtual PCI device. */
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union pci_bdf bdf;
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struct pci_pdev *pdev;
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union pci_cfgdata cfgdata;
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uint32_t flags;
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/* The bar info of the virtual PCI device. */
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uint32_t nr_bars; /* 6 for normal device, 2 for bridge, 1 for cardbus */
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struct pci_vbar vbars[PCI_BAR_COUNT];
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uint8_t prev_capoff; /* Offset of previous vPCI capability */
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uint8_t free_capoff; /* Next free offset to add vPCI capability */
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struct pci_msi msi;
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struct pci_msix msix;
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struct pci_cap_sriov sriov;
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/* Pointer to the SRIOV VF associated PF's vdev */
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struct pci_vdev *phyfun;
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/* Pointer to corresponding PCI device's vm_config */
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struct acrn_vm_pci_dev_config *pci_dev_config;
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/* Pointer to corressponding operations */
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const struct pci_vdev_ops *vdev_ops;
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/*
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* vdev in | HV | pre-VM | Service VM | post-VM
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* | | |vdev used by Service VM|vdev used by post-VM|
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* ----------------------------------------------------------------------------------------------------------
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* parent_user| NULL(HV) | NULL(HV) | NULL(HV) | NULL(HV) | vdev in Service VM
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* ----------------------------------------------------------------------------------------------------------
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* user | vdev in HV | vdev in pre-VM | vdev in Service VM | vdev in post-VM | vdev in post-VM
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*/
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struct pci_vdev *parent_user;
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struct pci_vdev *user; /* NULL means this device is not used or is a zombie VF */
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struct hlist_node link;
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void *priv_data;
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};
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union pci_cfg_addr_reg {
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uint32_t value;
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struct {
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uint32_t reg_num : 8; /* BITs 0-7, Register Number (BITs 0-1, always reserve to 0) */
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uint32_t bdf : 16; /* BITs 8-23, BDF Number */
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uint32_t resv : 7; /* BITs 24-30, Reserved */
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uint32_t enable : 1; /* BITs 31, Enable bit */
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} bits;
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};
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/* start address & end address of MMIO BAR */
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struct pci_mmio_res {
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uint64_t start;
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uint64_t end;
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};
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struct acrn_vpci {
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spinlock_t lock;
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union pci_cfg_addr_reg addr;
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struct pci_mmcfg_region pci_mmcfg;
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uint32_t pci_vdev_cnt;
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struct pci_mmio_res res32; /* 32-bit mmio start/end address */
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struct pci_mmio_res res64; /* 64-bit mmio start/end address */
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struct pci_vdev pci_vdevs[CONFIG_MAX_PCI_DEV_NUM];
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struct hlist_head vdevs_hlist_heads [VDEV_LIST_HASHSIZE];
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};
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struct acrn_vm;
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extern const struct pci_vdev_ops vhostbridge_ops;
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extern const struct pci_vdev_ops vpci_bridge_ops;
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int32_t init_vpci(struct acrn_vm *vm);
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void deinit_vpci(struct acrn_vm *vm);
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struct pci_vdev *pci_find_vdev(struct acrn_vpci *vpci, union pci_bdf vbdf);
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struct acrn_pcidev;
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int32_t vpci_assign_pcidev(struct acrn_vm *tgt_vm, struct acrn_pcidev *pcidev);
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int32_t vpci_deassign_pcidev(struct acrn_vm *tgt_vm, struct acrn_pcidev *pcidev);
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struct pci_vdev *vpci_init_vdev(struct acrn_vpci *vpci, struct acrn_vm_pci_dev_config *dev_config, struct pci_vdev *parent_pf_vdev);
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static inline bool is_pci_io_bar(struct pci_vbar *vbar)
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{
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return ((vbar->bar_type.io_space.indicator == 1U) && (!vbar->is_mem64hi));
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}
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static inline bool is_pci_mem_bar(struct pci_vbar *vbar)
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{
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return ((vbar->is_mem64hi) || ((vbar->bar_type.mem_space.indicator == 0U)));
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}
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/* Reserved PCI BAR type: 1.Memory bar with reserved memory type; 2.IO bar reserved bit is set */
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static inline bool is_pci_reserved_bar(struct pci_vbar *vbar)
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{
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return (((vbar->bar_type.mem_space.indicator == 0U) && ((vbar->bar_type.mem_space.mem_type & 0x1U) == 0x1U) && (!vbar->is_mem64hi)) ||
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((vbar->bar_type.io_space.indicator == 1U) && (vbar->bar_type.io_space.reserved == 1U)));
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}
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static inline bool is_pci_mem32_bar(struct pci_vbar *vbar)
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{
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return ((vbar->bar_type.mem_space.indicator == 0U) && (vbar->bar_type.mem_space.mem_type == 0U) && (!vbar->is_mem64hi));
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}
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static inline bool is_pci_mem64lo_bar(struct pci_vbar *vbar)
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{
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return ((vbar->bar_type.mem_space.indicator == 0U) && (vbar->bar_type.mem_space.mem_type == 2U) && (!vbar->is_mem64hi));
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}
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#endif /* VPCI_H_ */
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