457 lines
13 KiB
C
457 lines
13 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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/* Rate range 1 to 1000 or 1uSec to 1mSec */
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#define APIC_TIMER_MAX 0xffffffff
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#define HYPE_PERIOD_MAX 1000
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#define APIC_DIVIDE_BY_ONE 0x0b
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#define PIT_TARGET 0x3FFF
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/* xAPIC/x2APIC Interrupt Command Register (ICR) structure */
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union apic_icr {
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uint64_t value;
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struct {
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uint32_t lo_32;
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uint32_t hi_32;
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} value_32;
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struct {
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uint64_t vector:8;
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uint64_t delivery_mode:3;
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uint64_t destination_mode:1;
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uint64_t delivery_status:1;
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uint64_t rsvd_1:1;
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uint64_t level:1;
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uint64_t trigger_mode:1;
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uint64_t rsvd_2:2;
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uint64_t shorthand:2;
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uint64_t rsvd_3:12;
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uint64_t rsvd_4:32;
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} bits;
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struct {
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uint64_t rsvd_1:32;
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uint64_t rsvd_2:24;
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uint64_t dest_field:8;
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} x_bits;
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struct {
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uint64_t rsvd_1:32;
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uint64_t dest_field:32;
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} x2_bits;
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};
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/* xAPIC/x2APIC Interrupt Command Register (ICR) structure */
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union apic_lvt {
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uint32_t value;
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union {
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struct {
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uint32_t vector:8;
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uint32_t rsvd_1:4;
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uint32_t delivery_status:1;
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uint32_t rsvd_2:3;
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uint32_t mask:1;
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uint32_t mode:2;
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uint32_t rsvd_3:13;
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} timer;
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struct {
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uint32_t vector:8;
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uint32_t delivery_mode:3;
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uint32_t rsvd_1:1;
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uint32_t delivery_status:1;
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uint32_t rsvd_2:3;
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uint32_t mask:1;
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uint32_t rsvd_3:15;
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} cmci;
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struct {
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uint32_t vector:8;
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uint32_t delivery_mode:3;
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uint32_t rsvd_1:1;
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uint32_t delivery_status:1;
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uint32_t polarity:1;
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uint32_t remote_irr:1;
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uint32_t trigger_mode:1;
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uint32_t mask:1;
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uint32_t rsvd_2:15;
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} lint;
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struct {
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uint32_t vector:8;
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uint32_t rsvd_1:4;
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uint32_t delivery_status:1;
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uint32_t rsvd_2:3;
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uint32_t mask:1;
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uint32_t rsvd_3:15;
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} error;
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struct {
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uint32_t vector:8;
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uint32_t delivery_mode:3;
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uint32_t rsvd_1:1;
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uint32_t delivery_status:1;
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uint32_t rsvd_2:3;
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uint32_t mask:1;
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uint32_t rsvd_3:15;
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} pmc;
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struct {
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uint32_t vector:8;
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uint32_t delivery_mode:3;
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uint32_t rsvd_1:1;
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uint32_t delivery_status:1;
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uint32_t rsvd_2:3;
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uint32_t mask:1;
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uint32_t rsvd_3:15;
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} thermal;
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struct {
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uint32_t vector:8;
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uint32_t rsvd_1:4;
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uint32_t delivery_status:1;
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uint32_t rsvd_2:3;
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uint32_t mask:1;
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uint32_t rsvd_3:15;
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} common;
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} bits;
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};
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union lapic_base_msr {
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uint64_t value;
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struct {
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uint64_t rsvd_1:8;
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uint64_t bsp:1;
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uint64_t rsvd_2:1;
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uint64_t x2APIC_enable:1;
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uint64_t xAPIC_enable:1;
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uint64_t lapic_paddr:24;
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uint64_t rsvd_3:28;
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} fields;
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};
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struct lapic_info {
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int init_status;
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struct {
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uint64_t paddr;
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void *vaddr;
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} xapic;
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};
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static struct lapic_info lapic_info;
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static struct lapic_regs saved_lapic_regs;
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static union lapic_base_msr lapic_base_msr;
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static inline uint32_t read_lapic_reg32(uint32_t offset)
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{
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if (offset < 0x20 || offset > 0x3ff)
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return 0;
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return mmio_read_long(lapic_info.xapic.vaddr + offset);
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}
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inline void write_lapic_reg32(uint32_t offset, uint32_t value)
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{
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if (offset < 0x20 || offset > 0x3ff)
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return;
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mmio_write_long(value, lapic_info.xapic.vaddr + offset);
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}
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static void clear_lapic_isr(void)
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{
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uint64_t isr_reg = LAPIC_IN_SERVICE_REGISTER_0;
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/* This is a Intel recommended procedure and assures that the processor
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* does not get hung up due to already set "in-service" interrupts left
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* over from the boot loader environment. This actually occurs in real
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* life, therefore we will ensure all the in-service bits are clear.
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*/
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do {
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if (read_lapic_reg32(isr_reg) != 0U) {
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write_lapic_reg32(LAPIC_EOI_REGISTER, 0);
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continue;
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}
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isr_reg += 0x10;
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} while (isr_reg <= LAPIC_IN_SERVICE_REGISTER_7);
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}
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static void map_lapic(void)
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{
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/* At some point we may need to translate this paddr to a vaddr. 1:1
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* mapping for now.
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*/
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lapic_info.xapic.vaddr = HPA2HVA(lapic_info.xapic.paddr);
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}
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int early_init_lapic(void)
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{
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/* Get local APIC base address */
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lapic_base_msr.value = msr_read(MSR_IA32_APIC_BASE);
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/* Initialize globals only 1 time */
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if (lapic_info.init_status == false) {
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/* Get Local APIC physical address. */
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lapic_info.xapic.paddr = LAPIC_BASE;
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/* Map in the local xAPIC */
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map_lapic();
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lapic_info.init_status = true;
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}
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/* Check if xAPIC mode enabled */
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if (lapic_base_msr.fields.xAPIC_enable == 0) {
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/* Ensure in xAPIC mode */
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lapic_base_msr.fields.xAPIC_enable = 1;
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lapic_base_msr.fields.x2APIC_enable = 0;
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msr_write(MSR_IA32_APIC_BASE, lapic_base_msr.value);
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} else {
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/* Check if x2apic is disabled */
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ASSERT(lapic_base_msr.fields.x2APIC_enable == 0,
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"Disable X2APIC in BIOS");
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}
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return 0;
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}
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int init_lapic(uint16_t cpu_id)
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{
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/* Set the Logical Destination Register */
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write_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER,
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((1U << cpu_id) << 24));
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/* Set the Destination Format Register */
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write_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER, 0xf << 28);
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/* Mask all LAPIC LVT entries before enabling the local APIC */
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write_lapic_reg32(LAPIC_LVT_CMCI_REGISTER, LAPIC_LVT_MASK);
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write_lapic_reg32(LAPIC_LVT_TIMER_REGISTER, LAPIC_LVT_MASK);
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write_lapic_reg32(LAPIC_LVT_THERMAL_SENSOR_REGISTER, LAPIC_LVT_MASK);
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write_lapic_reg32(LAPIC_LVT_PMC_REGISTER, LAPIC_LVT_MASK);
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write_lapic_reg32(LAPIC_LVT_LINT0_REGISTER, LAPIC_LVT_MASK);
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write_lapic_reg32(LAPIC_LVT_LINT1_REGISTER, LAPIC_LVT_MASK);
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write_lapic_reg32(LAPIC_LVT_ERROR_REGISTER, LAPIC_LVT_MASK);
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/* Enable Local APIC */
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/* TODO: add spurious-interrupt handler */
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write_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER,
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LAPIC_SVR_APIC_ENABLE_MASK | LAPIC_SVR_VECTOR);
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/* Ensure there are no ISR bits set. */
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clear_lapic_isr();
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return 0;
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}
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void save_lapic(struct lapic_regs *regs)
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{
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regs->id = read_lapic_reg32(LAPIC_ID_REGISTER);
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regs->tpr = read_lapic_reg32(LAPIC_TASK_PRIORITY_REGISTER);
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regs->apr = read_lapic_reg32(LAPIC_ARBITRATION_PRIORITY_REGISTER);
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regs->ppr = read_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER);
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regs->ldr = read_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER);
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regs->dfr = read_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER);
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regs->tmr[0] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0);
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regs->tmr[1] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1);
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regs->tmr[2] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2);
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regs->tmr[3] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3);
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regs->tmr[4] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4);
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regs->tmr[5] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5);
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regs->tmr[6] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6);
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regs->tmr[7] = read_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7);
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regs->svr = read_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER);
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regs->lvtt = read_lapic_reg32(LAPIC_LVT_TIMER_REGISTER);
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regs->lvt0 = read_lapic_reg32(LAPIC_LVT_LINT0_REGISTER);
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regs->lvt1 = read_lapic_reg32(LAPIC_LVT_LINT1_REGISTER);
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regs->lvterr = read_lapic_reg32(LAPIC_LVT_ERROR_REGISTER);
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regs->ticr = read_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER);
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regs->tccr = read_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER);
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regs->tdcr = read_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER);
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}
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static void restore_lapic(struct lapic_regs *regs)
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{
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write_lapic_reg32(LAPIC_ID_REGISTER, regs->id);
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write_lapic_reg32(LAPIC_TASK_PRIORITY_REGISTER, regs->tpr);
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write_lapic_reg32(LAPIC_LOGICAL_DESTINATION_REGISTER, regs->ldr );
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write_lapic_reg32(LAPIC_DESTINATION_FORMAT_REGISTER, regs->dfr );
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write_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER, regs->svr );
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write_lapic_reg32(LAPIC_LVT_TIMER_REGISTER, regs->lvtt );
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write_lapic_reg32(LAPIC_LVT_LINT0_REGISTER, regs->lvt0 );
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write_lapic_reg32(LAPIC_LVT_LINT1_REGISTER, regs->lvt1 );
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write_lapic_reg32(LAPIC_LVT_ERROR_REGISTER, regs->lvterr );
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write_lapic_reg32(LAPIC_INITIAL_COUNT_REGISTER, regs->ticr );
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write_lapic_reg32(LAPIC_DIVIDE_CONFIGURATION_REGISTER, regs->tdcr );
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write_lapic_reg32(LAPIC_ARBITRATION_PRIORITY_REGISTER, regs->apr );
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write_lapic_reg32(LAPIC_PROCESSOR_PRIORITY_REGISTER, regs->ppr );
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write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_0, regs->tmr[0] );
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write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_1, regs->tmr[1] );
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write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_2, regs->tmr[2] );
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write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_3, regs->tmr[3] );
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write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_4, regs->tmr[4] );
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write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_5, regs->tmr[5] );
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write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_6, regs->tmr[6] );
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write_lapic_reg32(LAPIC_TRIGGER_MODE_REGISTER_7, regs->tmr[7] );
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write_lapic_reg32(LAPIC_CURRENT_COUNT_REGISTER, regs->tccr );
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}
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void suspend_lapic(void)
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{
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uint32_t val = 0;
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save_lapic(&saved_lapic_regs);
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/* disable APIC with software flag */
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val = read_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER);
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write_lapic_reg32(LAPIC_SPURIOUS_VECTOR_REGISTER,
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(~LAPIC_SVR_APIC_ENABLE_MASK) & val);
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}
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void resume_lapic(void)
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{
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msr_write(MSR_IA32_APIC_BASE, lapic_base_msr.value);
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/* ACPI software flag will be restored also */
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restore_lapic(&saved_lapic_regs);
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}
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void send_lapic_eoi(void)
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{
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write_lapic_reg32(LAPIC_EOI_REGISTER, 0);
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}
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static void wait_for_delivery(void)
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{
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union apic_icr tmp;
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do {
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tmp.value_32.lo_32 =
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read_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_0);
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} while (tmp.bits.delivery_status != 0U);
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}
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uint32_t get_cur_lapic_id(void)
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{
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uint32_t lapic_id;
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lapic_id = read_lapic_reg32(LAPIC_ID_REGISTER);
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lapic_id = (lapic_id >> 24);
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return lapic_id;
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}
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int
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send_startup_ipi(enum intr_cpu_startup_shorthand cpu_startup_shorthand,
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uint32_t cpu_startup_dest, uint64_t cpu_startup_start_address)
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{
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union apic_icr icr;
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uint8_t shorthand;
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int status = 0;
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if (cpu_startup_shorthand >= INTR_CPU_STARTUP_UNKNOWN)
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status = -EINVAL;
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ASSERT(status == 0, "Incorrect arguments");
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icr.value = 0;
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icr.bits.destination_mode = INTR_LAPIC_ICR_PHYSICAL;
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if (cpu_startup_shorthand == INTR_CPU_STARTUP_USE_DEST) {
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shorthand = INTR_LAPIC_ICR_USE_DEST_ARRAY;
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icr.x_bits.dest_field = per_cpu(lapic_id, cpu_startup_dest);
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} else { /* Use destination shorthand */
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shorthand = INTR_LAPIC_ICR_ALL_EX_SELF;
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icr.value_32.hi_32 = 0;
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}
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/* Assert INIT IPI */
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_1, icr.value_32.hi_32);
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icr.bits.shorthand = shorthand;
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icr.bits.delivery_mode = INTR_LAPIC_ICR_INIT;
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icr.bits.level = INTR_LAPIC_ICR_ASSERT;
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icr.bits.trigger_mode = INTR_LAPIC_ICR_LEVEL;
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_0, icr.value_32.lo_32);
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wait_for_delivery();
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/* Give 10ms for INIT sequence to complete for old processors.
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* Modern processors (family == 6) don't need to wait here.
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*/
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if (boot_cpu_data.x86 != 6)
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mdelay(10);
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/* De-assert INIT IPI */
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_1, icr.value_32.hi_32);
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icr.bits.level = INTR_LAPIC_ICR_DEASSERT;
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_0, icr.value_32.lo_32);
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wait_for_delivery();
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/* Send Start IPI with page number of secondary reset code */
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_1, icr.value_32.hi_32);
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icr.value_32.lo_32 = 0;
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icr.bits.shorthand = shorthand;
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icr.bits.delivery_mode = INTR_LAPIC_ICR_STARTUP;
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icr.bits.vector = ((uint64_t) cpu_startup_start_address) >> 12;
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_0, icr.value_32.lo_32);
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wait_for_delivery();
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if (boot_cpu_data.x86 == 6) /* 10us is enough for Modern processors */
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udelay(10);
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else /* 200us for old processors */
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udelay(200);
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/* Send another start IPI as per the Intel Arch specification */
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_1, icr.value_32.hi_32);
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_0, icr.value_32.lo_32);
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wait_for_delivery();
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return status;
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}
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void send_single_ipi(uint16_t pcpu_id, uint32_t vector)
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{
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uint32_t dest_lapic_id, hi_32, lo_32;
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/* Get the lapic ID of the destination processor. */
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dest_lapic_id = per_cpu(lapic_id, pcpu_id);
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/* Set the target processor. */
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hi_32 = dest_lapic_id << 24;
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/* Set the vector ID. */
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lo_32 = vector;
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/* Set the destination field to the target processor. */
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_1, hi_32);
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/* Write the vector ID to ICR. */
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_0, lo_32);
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wait_for_delivery();
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}
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int send_shorthand_ipi(uint8_t vector,
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enum intr_lapic_icr_shorthand shorthand,
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enum intr_lapic_icr_delivery_mode delivery_mode)
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{
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union apic_icr icr;
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int status = 0;
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if ((shorthand < INTR_LAPIC_ICR_SELF)
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|| (shorthand > INTR_LAPIC_ICR_ALL_EX_SELF)
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|| (delivery_mode > INTR_LAPIC_ICR_NMI))
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status = -EINVAL;
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ASSERT(status == 0, "Incorrect arguments");
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icr.value = 0;
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icr.bits.shorthand = shorthand;
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icr.bits.delivery_mode = delivery_mode;
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icr.bits.vector = vector;
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_1, icr.value_32.hi_32);
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write_lapic_reg32(LAPIC_INT_COMMAND_REGISTER_0, icr.value_32.lo_32);
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wait_for_delivery();
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return status;
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}
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