96 lines
3.6 KiB
C
96 lines
3.6 KiB
C
/*-
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* Copyright (c) 2012 NetApp, Inc.
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VMM_INSTRUCTION_EMUL_H_
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#define _VMM_INSTRUCTION_EMUL_H_
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/*
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* Callback functions to read and write memory regions.
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*/
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typedef int (*mem_region_read_t)(struct vcpu *vcpu, uint64_t gpa,
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uint64_t *rval, int rsize, void *arg);
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typedef int (*mem_region_write_t)(struct vcpu *vcpu, uint64_t gpa,
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uint64_t wval, int wsize, void *arg);
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/*
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* Emulate the decoded 'vie' instruction.
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*
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* The callbacks 'mrr' and 'mrw' emulate reads and writes to the memory region
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* containing 'gpa'. 'mrarg' is an opaque argument that is passed into the
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* callback functions.
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*
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* 'void *vm' should be 'struct vm *' when called from kernel context and
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* 'struct vmctx *' when called from user context.
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* s
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*/
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int vmm_emulate_instruction(struct vcpu *vcpu, uint64_t gpa, struct vie *vie,
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struct vm_guest_paging *paging, mem_region_read_t mrr,
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mem_region_write_t mrw, void *mrarg);
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int vie_update_register(struct vcpu *vcpu, enum vm_reg_name reg,
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uint64_t val, int size);
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/*
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* Returns 1 if an alignment check exception should be injected and 0 otherwise.
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*/
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int vie_alignment_check(int cpl, int operand_size, uint64_t cr0,
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uint64_t rflags, uint64_t gla);
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/* Returns 1 if the 'gla' is not canonical and 0 otherwise. */
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int vie_canonical_check(enum vm_cpu_mode cpu_mode, uint64_t gla);
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uint64_t vie_size2mask(int size);
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int vie_calculate_gla(enum vm_cpu_mode cpu_mode, enum vm_reg_name seg,
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struct seg_desc *desc, uint64_t off, int length, int addrsize, int prot,
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uint64_t *gla);
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int vie_init(struct vie *vie, struct vcpu *vcpu);
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/*
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* Decode the instruction fetched into 'vie' so it can be emulated.
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*
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* 'gla' is the guest linear address provided by the hardware assist
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* that caused the nested page table fault. It is used to verify that
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* the software instruction decoding is in agreement with the hardware.
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*
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* Some hardware assists do not provide the 'gla' to the hypervisor.
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* To skip the 'gla' verification for this or any other reason pass
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* in VIE_INVALID_GLA instead.
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*/
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#define VIE_INVALID_GLA (1UL << 63) /* a non-canonical address */
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int
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__decode_instruction(enum vm_cpu_mode cpu_mode, int cs_d, struct vie *vie);
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int emulate_instruction(struct vcpu *vcpu);
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int decode_instruction(struct vcpu *vcpu);
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#endif /* _VMM_INSTRUCTION_EMUL_H_ */
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