42 lines
1.1 KiB
C
42 lines
1.1 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IOAPIC_H
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#define IOAPIC_H
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/*
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* IOAPIC_MAX_LINES is architecturally defined.
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* The usable RTEs may be a subset of the total on a per IO APIC basis.
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*/
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#define IOAPIC_MAX_LINES 120U
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#define NR_LEGACY_IRQ 16U
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#define NR_LEGACY_PIN NR_LEGACY_IRQ
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#define NR_MAX_GSI (CONFIG_NR_IOAPICS * IOAPIC_MAX_LINES)
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#define GSI_MASK_IRQ(irq) irq_gsi_mask_unmask((irq), true)
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#define GSI_UNMASK_IRQ(irq) irq_gsi_mask_unmask((irq), false)
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void setup_ioapic_irqs(void);
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bool irq_is_gsi(uint32_t irq);
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uint32_t irq_gsi_num(void);
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uint8_t irq_to_pin(uint32_t irq);
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uint32_t pin_to_irq(uint8_t pin);
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void irq_gsi_mask_unmask(uint32_t irq, bool mask);
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void ioapic_set_rte(uint32_t irq, union ioapic_rte rte);
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void ioapic_get_rte(uint32_t irq, union ioapic_rte *rte);
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void suspend_ioapic(void);
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void resume_ioapic(void);
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extern uint8_t pic_ioapic_pin_map[NR_LEGACY_PIN];
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#ifdef HV_DEBUG
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int get_ioapic_info(char *str_arg, int str_max_len);
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#endif /* HV_DEBUG */
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#endif /* IOAPIC_H */
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