86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VM0_BOOT_H
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#define VM0_BOOT_H
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#ifdef ASSEMBLER
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#define BOOT_CTX_CR0_OFFSET 0
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#define BOOT_CTX_CR3_OFFSET 8
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#define BOOT_CTX_CR4_OFFSET 16
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#define BOOT_CTX_IDT_OFFSET 24
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#define BOOT_CTX_GDT_OFFSET 34
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#define BOOT_CTX_LDT_SEL_OFFSET 44
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#define BOOT_CTX_TR_SEL_OFFSET 46
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#define BOOT_CTX_CS_SEL_OFFSET 48
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#define BOOT_CTX_SS_SEL_OFFSET 50
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#define BOOT_CTX_DS_SEL_OFFSET 52
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#define BOOT_CTX_ES_SEL_OFFSET 54
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#define BOOT_CTX_FS_SEL_OFFSET 56
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#define BOOT_CTX_GS_SEL_OFFSET 58
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#define BOOT_CTX_CS_AR_OFFSET 60
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#define BOOT_CTX_EFER_LOW_OFFSET 64
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#define BOOT_CTX_EFER_HIGH_OFFSET 68
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#else
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#include <gpr.h>
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#define BOOT_CTX_CR0_OFFSET 0U
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#define BOOT_CTX_CR3_OFFSET 8U
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#define BOOT_CTX_CR4_OFFSET 16U
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#define BOOT_CTX_IDT_OFFSET 24U
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#define BOOT_CTX_GDT_OFFSET 34U
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#define BOOT_CTX_LDT_SEL_OFFSET 44U
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#define BOOT_CTX_TR_SEL_OFFSET 46U
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#define BOOT_CTX_CS_SEL_OFFSET 48U
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#define BOOT_CTX_SS_SEL_OFFSET 50U
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#define BOOT_CTX_DS_SEL_OFFSET 52U
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#define BOOT_CTX_ES_SEL_OFFSET 54U
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#define BOOT_CTX_FS_SEL_OFFSET 56U
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#define BOOT_CTX_GS_SEL_OFFSET 58U
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#define BOOT_CTX_CS_AR_OFFSET 60U
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#define BOOT_CTX_EFER_LOW_OFFSET 64U
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#define BOOT_CTX_EFER_HIGH_OFFSET 68U
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struct dt_addr {
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uint16_t limit;
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uint64_t base;
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} __attribute__((packed));
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struct boot_ctx {
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uint64_t cr0;
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uint64_t cr3;
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uint64_t cr4;
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struct dt_addr idt;
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struct dt_addr gdt;
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uint16_t ldt_sel;
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uint16_t tr_sel;
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/* align the order to ext_context */
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uint16_t cs_sel;
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uint16_t ss_sel;
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uint16_t ds_sel;
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uint16_t es_sel;
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uint16_t fs_sel;
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uint16_t gs_sel;
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uint32_t cs_ar;
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uint64_t ia32_efer;
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#ifdef CONFIG_EFI_STUB
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struct cpu_gp_regs gprs;
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uint64_t rip;
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uint64_t rflags;
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void *rsdp;
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void *ap_trampoline_buf;
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#endif
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}__attribute__((packed));
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#ifdef CONFIG_EFI_STUB
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void *get_rsdp_from_uefi(void);
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void *get_ap_trampoline_buf(void);
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#endif
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#endif /* ASSEMBLER */
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#endif /* VM0_BOOT_H */
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