32 lines
578 B
C
32 lines
578 B
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _VGPR_H_
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#define _VGPR_H_
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/* General-purpose register layout aligned with the general-purpose register idx
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* when vmexit, such as vmexit due to CR access, refer to SMD Vol.3C 27-6.
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*/
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struct cpu_gp_regs {
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uint64_t rax;
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uint64_t rcx;
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uint64_t rdx;
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uint64_t rbx;
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uint64_t rsp;
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uint64_t rbp;
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uint64_t rsi;
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uint64_t rdi;
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uint64_t r8;
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uint64_t r9;
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uint64_t r10;
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uint64_t r11;
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uint64_t r12;
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uint64_t r13;
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uint64_t r14;
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uint64_t r15;
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};
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#endif
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