acrn-hypervisor/devicemodel/hw/pci/platform_gsi_info.c

130 lines
2.6 KiB
C

/*
* Copyright (C) 2018 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "pci_core.h"
#define APL_MRB 1
#ifdef APL_MRB
struct gsi_dev gsi_dev_mapping_tables[] = {
{"timer", 0},
{"keyboard", 1},
{"hpet0", 2},
{"00:1b.0", 3},
{"00:18.0", 4},
{"00:18.1", 5},
{"00:18.2", 6},
{"00:18.3", 7},
{"rtc", 8},
{"acpi", 9},
{"00:15.1", 13},
{"gpio_ctlr", 14},
{"00:15.0", 17},
{"00:02.0", 19},
{"00:12.0", 19},
{"00:0f.0", 20},
{"00:1f.1", 20},
{"02:00.0", 20},
{"00:03.0", 21},
{"03:00.0", 21},
{"00:00.1", 24},
{"00:0e.0", 25},
{"00:11.0", 26},
{"00:16.0", 27},
{"00:16.1", 28},
{"00:16.2", 29},
{"00:16.3", 30},
{"00:17.0", 31},
{"00:17.1", 32},
{"00:17.2", 33},
{"00:17.3", 34},
{"00:19.0", 35},
{"00:19.1", 36},
{"00:19.2", 37},
{"00:1c.0", 39},
{"pmc_ipc", 40},
{"00:1e.0", 42},
{"gpio_pin_00", 50},
{"gpio_pin_01", 51},
{"gpio_pin_02", 52},
{"gpio_pin_03", 53},
{"gpio_pin_04", 54},
{"gpio_pin_05", 55},
{"gpio_pin_06", 56},
{"gpio_pin_07", 57},
{"gpio_pin_08", 58},
{"gpio_pin_09", 59},
{"gpio_pin_10", 60},
{"gpio_pin_11", 61},
{"gpio_pin_12", 62},
{"gpio_pin_13", 63},
{"gpio_pin_14", 64},
{"gpio_pin_15", 65},
{"gpio_pin_16", 66},
{"gpio_pin_17", 67},
{"gpio_pin_18", 68},
{"gpio_pin_19", 69},
{"gpio_pin_20", 70},
{"gpio_pin_21", 71},
{"gpio_pin_22", 72},
{"gpio_pin_23", 73},
{"gpio_pin_24", 74},
{"gpio_pin_25", 75},
{"gpio_pin_26", 76},
{"gpio_pin_27", 77},
{"gpio_pin_28", 78},
{"gpio_pin_29", 79},
{"gpio_pin_30", 80},
{"gpio_pin_31", 81},
{"gpio_pin_32", 82},
{"gpio_pin_33", 83},
{"gpio_pin_34", 84},
{"gpio_pin_35", 85},
{"gpio_pin_36", 86},
{"gpio_pin_37", 87},
{"gpio_pin_38", 88},
{"gpio_pin_39", 89},
{"gpio_pin_40", 90},
{"gpio_pin_41", 91},
{"gpio_pin_42", 92},
{"gpio_pin_43", 93},
{"gpio_pin_44", 94},
{"gpio_pin_45", 95},
{"gpio_pin_46", 96},
{"gpio_pin_47", 97},
{"gpio_pin_48", 98},
{"gpio_pin_49", 99},
{"gpio_pin_50", 100},
{"gpio_pin_51", 101},
{"gpio_pin_52", 102},
{"gpio_pin_53", 103},
{"gpio_pin_54", 104},
{"gpio_pin_55", 105},
{"gpio_pin_56", 106},
{"gpio_pin_57", 107},
{"gpio_pin_58", 108},
{"gpio_pin_59", 109},
{"gpio_pin_60", 110},
{"gpio_pin_61", 111},
{"gpio_pin_62", 112},
{"gpio_pin_63", 113},
{"gpio_pin_64", 114},
{"gpio_pin_65", 115},
{"gpio_pin_66", 116},
{"gpio_pin_67", 117},
{"gpio_pin_68", 118},
{"gpio_pin_69", 119},
};
#else
/*
* Assume there is no GSI sharing if no hardcoded info is provided in
* gsi_sharing_tables.
*/
struct gsi_dev gsi_dev_mapping_tables[] = {};
#endif
int num_gsi_dev_mapping_tables = ARRAY_SIZE(gsi_dev_mapping_tables);