Fei Li bc5c3a0bb7 hv: vpci: modify Interrupt Line Register as writable ... According to PCIe Spec, for a RW register bits, If the optional feature that is associated with the bits is not implemented, the bits are permitted to be hardwired to 0b. However Zephyr would use INTx Line Register as writable even this PCI device has no INTx, so emulate INTx Line Register as writable. Tracked-On: #6330 Signed-off-by: Fei Li <fei1.li@intel.com>		2021-08-03 11:01:24 +08:00
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vpci	hv: vpci: modify Interrupt Line Register as writable	2021-08-03 11:01:24 +08:00
io_req.c	hv: dm: Use new I/O request data structures	2021-07-15 11:53:54 +08:00
mmio_dev.c	dm: Use new MMIO device passthrough management ioctls	2021-07-15 11:53:54 +08:00
vgpio.c	dm: Use new MMIO device passthrough management ioctls	2021-07-15 11:53:54 +08:00
vioapic.c	hv: dm: Use new I/O request data structures	2021-07-15 11:53:54 +08:00
vpic.c	hv: dm: Use new I/O request data structures	2021-07-15 11:53:54 +08:00
vrtc.c	hv: dm: Use new I/O request data structures	2021-07-15 11:53:54 +08:00
vuart.c	hv: dm: Use new I/O request data structures	2021-07-15 11:53:54 +08:00