53 lines
1.7 KiB
C
53 lines
1.7 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _TPM_H_
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#define _TPM_H_
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#define TPM_CRB_MMIO_ADDR 0xFED40000UL
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#define TPM_CRB_MMIO_SIZE 0x1000U
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/* TPM CRB registers */
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enum {
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CRB_REGS_LOC_STATE = TPM_CRB_MMIO_ADDR + 0x00,
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CRB_REGS_RESERVED0 = TPM_CRB_MMIO_ADDR + 0x04,
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CRB_REGS_LOC_CTRL = TPM_CRB_MMIO_ADDR + 0x08,
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CRB_REGS_LOC_STS = TPM_CRB_MMIO_ADDR + 0x0C,
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CRB_REGS_RESERVED1 = TPM_CRB_MMIO_ADDR + 0x10,
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CRB_REGS_INTF_ID_LO = TPM_CRB_MMIO_ADDR + 0x30,
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CRB_REGS_INTF_ID_HI = TPM_CRB_MMIO_ADDR + 0x34,
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CRB_REGS_CTRL_EXT_LO = TPM_CRB_MMIO_ADDR + 0x38,
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CRB_REGS_CTRL_EXT_HI = TPM_CRB_MMIO_ADDR + 0x3C,
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CRB_REGS_CTRL_REQ = TPM_CRB_MMIO_ADDR + 0x40,
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CRB_REGS_CTRL_STS = TPM_CRB_MMIO_ADDR + 0x44,
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CRB_REGS_CTRL_CANCEL = TPM_CRB_MMIO_ADDR + 0x48,
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CRB_REGS_CTRL_START = TPM_CRB_MMIO_ADDR + 0x4C,
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CRB_REGS_CTRL_INT_ENABLE = TPM_CRB_MMIO_ADDR + 0x50,
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CRB_REGS_CTRL_INT_STS = TPM_CRB_MMIO_ADDR + 0x54,
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CRB_REGS_CTRL_CMD_SIZE = TPM_CRB_MMIO_ADDR + 0x58,
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CRB_REGS_CTRL_CMD_PA_LO = TPM_CRB_MMIO_ADDR + 0x5C,
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CRB_REGS_CTRL_CMD_PA_HI = TPM_CRB_MMIO_ADDR + 0x60,
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CRB_REGS_CTRL_RSP_SIZE = TPM_CRB_MMIO_ADDR + 0x64,
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CRB_REGS_CTRL_RSP_PA = TPM_CRB_MMIO_ADDR + 0x68,
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CRB_DATA_BUFFER = TPM_CRB_MMIO_ADDR + 0x80
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};
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#define TPM_CRB_REG_SIZE ((CRB_DATA_BUFFER) - (TPM_CRB_MMIO_ADDR))
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#define TPM_CRB_DATA_BUFFER_SIZE ((TPM_CRB_MMIO_SIZE) - (TPM_CRB_REG_SIZE))
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/* APIs by tpm.c */
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/* Initialize Virtual TPM2 */
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void init_vtpm2(struct vmctx *ctx);
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/* Deinitialize Virtual TPM2 */
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void deinit_vtpm2(struct vmctx *ctx);
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/* Parse Virtual TPM option from command line */
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int acrn_parse_vtpm2(char *arg);
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#endif
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