274 lines
6.7 KiB
C
274 lines
6.7 KiB
C
/*
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* Copyright (C) <2018> Intel Corporation
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <acrn_common.h>
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#include <asm/default_acpi_info.h>
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#include <platform_acpi_info.h>
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#include <asm/per_cpu.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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#include <asm/pgtable.h>
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#include <asm/host_pm.h>
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#include <asm/trampoline.h>
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#include <asm/vmx.h>
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#include <console.h>
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#include <asm/ioapic.h>
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#include <asm/vtd.h>
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#include <asm/lapic.h>
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#include <asm/tsc.h>
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#include <delay.h>
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struct cpu_context cpu_ctx;
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/* The values in this structure should come from host ACPI table */
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static struct pm_s_state_data host_pm_s_state = {
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.pm1a_evt = {
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.space_id = PM1A_EVT_SPACE_ID,
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.bit_width = PM1A_EVT_BIT_WIDTH,
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.bit_offset = PM1A_EVT_BIT_OFFSET,
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.access_size = PM1A_EVT_ACCESS_SIZE,
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.address = PM1A_EVT_ADDRESS
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},
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.pm1b_evt = {
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.space_id = PM1B_EVT_SPACE_ID,
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.bit_width = PM1B_EVT_BIT_WIDTH,
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.bit_offset = PM1B_EVT_BIT_OFFSET,
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.access_size = PM1B_EVT_ACCESS_SIZE,
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.address = PM1B_EVT_ADDRESS
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},
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.pm1a_cnt = {
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.space_id = PM1A_CNT_SPACE_ID,
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.bit_width = PM1A_CNT_BIT_WIDTH,
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.bit_offset = PM1A_CNT_BIT_OFFSET,
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.access_size = PM1A_CNT_ACCESS_SIZE,
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.address = PM1A_CNT_ADDRESS
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},
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.pm1b_cnt = {
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.space_id = PM1B_CNT_SPACE_ID,
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.bit_width = PM1B_CNT_BIT_WIDTH,
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.bit_offset = PM1B_CNT_BIT_OFFSET,
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.access_size = PM1B_CNT_ACCESS_SIZE,
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.address = PM1B_CNT_ADDRESS
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},
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.s3_pkg = {
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.val_pm1a = S3_PKG_VAL_PM1A,
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.val_pm1b = S3_PKG_VAL_PM1B,
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.reserved = S3_PKG_RESERVED
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},
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.s5_pkg = {
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.val_pm1a = S5_PKG_VAL_PM1A,
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.val_pm1b = S5_PKG_VAL_PM1B,
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.reserved = S5_PKG_RESERVED
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},
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.wake_vector_32 = (uint32_t *)WAKE_VECTOR_32,
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.wake_vector_64 = (uint64_t *)WAKE_VECTOR_64
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};
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/* host reset register defined in ACPI */
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static struct acpi_reset_reg host_reset_reg = {
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.reg = {
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.space_id = RESET_REGISTER_SPACE_ID,
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.bit_width = RESET_REGISTER_BIT_WIDTH,
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.bit_offset = RESET_REGISTER_BIT_OFFSET,
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.access_size = RESET_REGISTER_ACCESS_SIZE,
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.address = RESET_REGISTER_ADDRESS,
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},
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.val = RESET_REGISTER_VALUE
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};
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struct pm_s_state_data *get_host_sstate_data(void)
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{
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return &host_pm_s_state;
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}
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struct acpi_reset_reg *get_host_reset_reg_data(void)
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{
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return &host_reset_reg;
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}
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void restore_msrs(void)
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{
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#ifdef STACK_PROTECTOR
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struct stack_canary *psc = &get_cpu_var(stk_canary);
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msr_write(MSR_IA32_FS_BASE, (uint64_t)psc);
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#endif
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}
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static void acpi_gas_write(const struct acrn_acpi_generic_address *gas, uint32_t val)
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{
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uint16_t val16 = (uint16_t)val;
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if (gas->space_id == SPACE_SYSTEM_MEMORY) {
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mmio_write16(val16, hpa2hva(gas->address));
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} else {
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pio_write16(val16, (uint16_t)gas->address);
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}
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}
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static uint32_t acpi_gas_read(const struct acrn_acpi_generic_address *gas)
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{
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uint32_t ret = 0U;
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if (gas->space_id == SPACE_SYSTEM_MEMORY) {
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ret = mmio_read16(hpa2hva(gas->address));
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} else {
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ret = pio_read16((uint16_t)gas->address);
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}
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return ret;
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}
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/* This function supports enter S3 or S5 according to the value given to pm1a_cnt_val and pm1b_cnt_val */
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void do_acpi_sx(const struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val)
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{
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uint32_t s1, s2;
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acpi_gas_write(&(sstate_data->pm1a_cnt), pm1a_cnt_val);
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if (sstate_data->pm1b_cnt.address != 0U) {
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acpi_gas_write(&(sstate_data->pm1b_cnt), pm1b_cnt_val);
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}
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do {
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/* polling PM1 state register to detect wether
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* the Sx state enter is interrupted by wakeup event.
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*/
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s1 = acpi_gas_read(&(sstate_data->pm1a_evt));
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if (sstate_data->pm1b_evt.address != 0U) {
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s2 = acpi_gas_read(&(sstate_data->pm1b_evt));
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s1 |= s2;
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}
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/* According to ACPI spec 4.8.3.1.1 PM1 state register, the bit
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* WAK_STS(bit 15) is set if system will transition to working
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* state.
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*/
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} while ((s1 & (1U << BIT_WAK_STS)) == 0U);
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}
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static uint32_t system_pm1a_cnt_val, system_pm1b_cnt_val;
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void save_s5_reg_val(uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val)
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{
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system_pm1a_cnt_val = pm1a_cnt_val;
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system_pm1b_cnt_val = pm1b_cnt_val;
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}
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void shutdown_system(void)
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{
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struct pm_s_state_data *sx_data = get_host_sstate_data();
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do_acpi_sx(sx_data, system_pm1a_cnt_val, system_pm1b_cnt_val);
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}
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static void suspend_tsc(__unused void *data)
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{
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per_cpu(tsc_suspend, get_pcpu_id()) = rdtsc();
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}
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static void resume_tsc(__unused void *data)
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{
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msr_write(MSR_IA32_TIME_STAMP_COUNTER, per_cpu(tsc_suspend, get_pcpu_id()));
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}
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void host_enter_s3(const struct pm_s_state_data *sstate_data, uint32_t pm1a_cnt_val, uint32_t pm1b_cnt_val)
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{
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uint64_t pmain_entry_saved;
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stac();
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/* set ACRN wakeup vec instead */
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*(sstate_data->wake_vector_32) = (uint32_t)get_trampoline_start16_paddr();
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clac();
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/* Save TSC on all PCPU */
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smp_call_function(get_active_pcpu_bitmap(), suspend_tsc, NULL);
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/* offline all APs */
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stop_pcpus();
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stac();
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/* Save default main entry and we will restore it after
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* back from S3. So the AP online could jmp to correct
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* main entry.
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*/
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pmain_entry_saved = read_trampoline_sym(main_entry);
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/* Set the main entry for resume from S3 state */
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write_trampoline_sym(main_entry, (uint64_t)restore_s3_context);
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clac();
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CPU_IRQ_DISABLE_ON_CONFIG();
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vmx_off();
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suspend_console();
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suspend_ioapic();
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suspend_iommu();
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suspend_lapic();
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asm_enter_s3(sstate_data, pm1a_cnt_val, pm1b_cnt_val);
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resume_lapic();
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resume_iommu();
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resume_ioapic();
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vmx_on();
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CPU_IRQ_ENABLE_ON_CONFIG();
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/* restore the default main entry */
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stac();
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write_trampoline_sym(main_entry, pmain_entry_saved);
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clac();
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/* online all APs again */
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if (!start_pcpus(AP_MASK)) {
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panic("Failed to start all APs!");
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}
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/* Restore TSC on all PCPU
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* Caution: There should no timer setup before TSC resumed.
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*/
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smp_call_function(get_active_pcpu_bitmap(), resume_tsc, NULL);
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/* console must be resumed after TSC restored since it will setup timer base on TSC */
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resume_console();
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}
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void reset_host(void)
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{
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struct acrn_acpi_generic_address *gas = &(host_reset_reg.reg);
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/* TODO: gracefully shut down all guests before doing host reset. */
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/*
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* Assumption:
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* The platform we are running must support at least one of reset method:
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* - ACPI reset
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* - 0xcf9 reset
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*
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* UEFI more likely sets the reset value as 0x6 (not 0xe) for 0xcf9 port.
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* This asserts PLTRST# to reset devices on the platform, but not the
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* SLP_S3#/4#/5# signals, which power down the systems. This might not be
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* enough for us.
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*/
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if ((gas->space_id == SPACE_SYSTEM_IO) &&
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(gas->bit_width == 8U) && (gas->bit_offset == 0U) &&
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(gas->address != 0U) && (gas->address != 0xcf9U)) {
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pio_write8(host_reset_reg.val, (uint16_t)host_reset_reg.reg.address);
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} else {
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/* making sure bit 2 (RST_CPU) is '0', when the reset command is issued. */
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pio_write8(0x2U, 0xcf9U);
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udelay(50U);
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pio_write8(0xeU, 0xcf9U);
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}
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pr_fatal("%s(): can't reset host.", __func__);
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while (1) {
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asm_pause();
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}
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}
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