281 lines
7.1 KiB
C
281 lines
7.1 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VMM_H_
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#define _VMM_H_
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#include "types.h"
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#include "vhm_ioctl_defs.h"
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/*
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* Entries in the Interrupt Descriptor Table (IDT)
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*/
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#define IDT_DE 0 /* #DE: Divide Error */
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#define IDT_DB 1 /* #DB: Debug */
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#define IDT_NMI 2 /* Nonmaskable External Interrupt */
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#define IDT_BP 3 /* #BP: Breakpoint */
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#define IDT_OF 4 /* #OF: Overflow */
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#define IDT_BR 5 /* #BR: Bound Range Exceeded */
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#define IDT_UD 6 /* #UD: Undefined/Invalid Opcode */
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#define IDT_NM 7 /* #NM: No Math Coprocessor */
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#define IDT_DF 8 /* #DF: Double Fault */
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#define IDT_FPUGP 9 /* Coprocessor Segment Overrun */
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#define IDT_TS 10 /* #TS: Invalid TSS */
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#define IDT_NP 11 /* #NP: Segment Not Present */
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#define IDT_SS 12 /* #SS: Stack Segment Fault */
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#define IDT_GP 13 /* #GP: General Protection Fault */
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#define IDT_PF 14 /* #PF: Page Fault */
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#define IDT_MF 16 /* #MF: FPU Floating-Point Error */
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#define IDT_AC 17 /* #AC: Alignment Check */
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#define IDT_MC 18 /* #MC: Machine Check */
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#define IDT_XF 19 /* #XF: SIMD Floating-Point Exception */
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enum vm_suspend_how {
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VM_SUSPEND_NONE,
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VM_SUSPEND_SYSTEM_RESET,
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VM_SUSPEND_FULL_RESET,
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VM_SUSPEND_POWEROFF,
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VM_SUSPEND_SUSPEND,
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VM_SUSPEND_HALT,
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VM_SUSPEND_TRIPLEFAULT,
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VM_SUSPEND_LAST
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};
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/*
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* Identifiers for architecturally defined registers.
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*/
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enum cpu_reg_name {
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CPU_REG_RAX,
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CPU_REG_RBX,
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CPU_REG_RCX,
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CPU_REG_RDX,
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CPU_REG_RSI,
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CPU_REG_RDI,
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CPU_REG_RBP,
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CPU_REG_R8,
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CPU_REG_R9,
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CPU_REG_R10,
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CPU_REG_R11,
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CPU_REG_R12,
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CPU_REG_R13,
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CPU_REG_R14,
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CPU_REG_R15,
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CPU_REG_CR0,
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CPU_REG_CR3,
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CPU_REG_CR4,
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CPU_REG_DR7,
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CPU_REG_RSP,
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CPU_REG_RIP,
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CPU_REG_RFLAGS,
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CPU_REG_ES,
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CPU_REG_CS,
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CPU_REG_SS,
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CPU_REG_DS,
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CPU_REG_FS,
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CPU_REG_GS,
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CPU_REG_LDTR,
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CPU_REG_TR,
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CPU_REG_IDTR,
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CPU_REG_GDTR,
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CPU_REG_EFER,
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CPU_REG_CR2,
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CPU_REG_PDPTE0,
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CPU_REG_PDPTE1,
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CPU_REG_PDPTE2,
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CPU_REG_PDPTE3,
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CPU_REG_LAST
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};
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#define VM_INTINFO_VECTOR(info) ((info) & 0xff)
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#define VM_INTINFO_DEL_ERRCODE 0x800
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#define VM_INTINFO_RSVD 0x7ffff000
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#define VM_INTINFO_VALID 0x80000000
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#define VM_INTINFO_TYPE 0x700
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#define VM_INTINFO_HWINTR (0 << 8)
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#define VM_INTINFO_NMI (2 << 8)
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#define VM_INTINFO_HWEXCEPTION (3 << 8)
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#define VM_INTINFO_SWINTR (4 << 8)
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#define VM_MAXCPU 16 /* maximum virtual cpus */
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/*
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* Identifiers for optional vmm capabilities
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*/
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enum vm_cap_type {
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VM_CAP_HALT_EXIT,
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VM_CAP_MTRAP_EXIT,
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VM_CAP_PAUSE_EXIT,
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VM_CAP_UNRESTRICTED_GUEST,
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VM_CAP_ENABLE_INVPCID,
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VM_CAP_MAX
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};
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enum vm_intr_trigger {
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EDGE_TRIGGER,
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LEVEL_TRIGGER
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};
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/*
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* The 'access' field has the format specified in Table 21-2 of the Intel
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* Architecture Manual vol 3b.
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*
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* XXX The contents of the 'access' field are architecturally defined except
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* bit 16 - Segment Unusable.
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*/
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struct seg_desc {
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uint64_t base;
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uint32_t limit;
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uint32_t access;
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};
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#define SEG_DESC_TYPE(access) ((access) & 0x001f)
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#define SEG_DESC_DPL(access) (((access) >> 5) & 0x3)
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#define SEG_DESC_PRESENT(access) (((access) & 0x0080) ? 1 : 0)
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#define SEG_DESC_DEF32(access) (((access) & 0x4000) ? 1 : 0)
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#define SEG_DESC_GRANULARITY(access) (((access) & 0x8000) ? 1 : 0)
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#define SEG_DESC_UNUSABLE(access) (((access) & 0x10000) ? 1 : 0)
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enum vm_cpu_mode {
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CPU_MODE_REAL,
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CPU_MODE_PROTECTED,
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CPU_MODE_COMPATIBILITY, /* IA-32E mode (CS.L = 0) */
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CPU_MODE_64BIT, /* IA-32E mode (CS.L = 1) */
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};
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enum vm_paging_mode {
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PAGING_MODE_FLAT,
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PAGING_MODE_32,
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PAGING_MODE_PAE,
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PAGING_MODE_64,
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};
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struct vm_guest_paging {
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uint64_t cr3;
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int cpl;
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enum vm_cpu_mode cpu_mode;
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enum vm_paging_mode paging_mode;
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};
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/*
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* The data structures 'vie' and 'vie_op' are meant to be opaque to the
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* consumers of instruction decoding. The only reason why their contents
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* need to be exposed is because they are part of the 'vhm_request' structure.
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*/
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struct vie_op {
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uint8_t op_byte; /* actual opcode byte */
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uint8_t op_type; /* type of operation (e.g. MOV) */
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uint16_t op_flags;
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};
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#define VIE_INST_SIZE 15
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struct vie {
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uint8_t inst[VIE_INST_SIZE]; /* instruction bytes */
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uint8_t num_valid; /* size of the instruction */
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uint8_t num_processed;
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uint8_t addrsize:4, opsize:4; /* address and operand sizes */
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uint8_t rex_w:1, /* REX prefix */
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rex_r:1,
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rex_x:1,
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rex_b:1,
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rex_present:1,
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repz_present:1, /* REP/REPE/REPZ prefix */
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repnz_present:1, /* REPNE/REPNZ prefix */
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opsize_override:1, /* Operand size override */
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addrsize_override:1, /* Address size override */
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segment_override:1; /* Segment override */
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uint8_t mod:2, /* ModRM byte */
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reg:4,
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rm:4;
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uint8_t ss:2, /* SIB byte */
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index:4,
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base:4;
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uint8_t disp_bytes;
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uint8_t imm_bytes;
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uint8_t scale;
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int base_register; /* CPU_REG_xyz */
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int index_register; /* CPU_REG_xyz */
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int segment_register; /* CPU_REG_xyz */
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int64_t displacement; /* optional addr displacement */
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int64_t immediate; /* optional immediate operand */
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uint8_t decoded; /* set to 1 if successfully decoded */
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struct vie_op op; /* opcode description */
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};
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enum vm_exitcode {
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VM_EXITCODE_INOUT = 0,
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VM_EXITCODE_MMIO_EMUL,
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VM_EXITCODE_PCI_CFG,
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VM_EXITCODE_MAX
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};
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struct vm_inout {
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uint16_t bytes:3; /* 1 or 2 or 4 */
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uint16_t in:1;
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uint16_t string:1;
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uint16_t rep:1;
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uint16_t port;
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uint32_t eax; /* valid for out */
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};
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struct vm_inout_str {
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struct vm_inout inout; /* must be the first element */
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struct vm_guest_paging paging;
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uint64_t rflags;
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uint64_t cr0;
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uint64_t index;
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uint64_t count; /* rep=1 (%rcx), rep=0 (1) */
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int addrsize;
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enum cpu_reg_name seg_name;
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struct seg_desc seg_desc;
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};
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enum task_switch_reason {
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TSR_CALL,
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TSR_IRET,
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TSR_JMP,
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TSR_IDT_GATE, /* task gate in IDT */
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};
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struct vm_task_switch {
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uint16_t tsssel; /* new TSS selector */
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int ext; /* task switch due to external event */
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uint32_t errcode;
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int errcode_valid; /* push 'errcode' on the new stack */
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enum task_switch_reason reason;
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struct vm_guest_paging paging;
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};
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#endif /* _VMM_H_ */
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