441 lines
10 KiB
C
441 lines
10 KiB
C
/*-
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* Copyright (c) 2012 NetApp, Inc.
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <types.h>
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#include <pci.h>
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#include <uart16550.h>
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#include <console.h>
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#include <vuart.h>
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#include <vm.h>
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#include <logmsg.h>
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static uint32_t vuart_com_irq = CONFIG_COM_IRQ;
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static uint16_t vuart_com_base = CONFIG_COM_BASE;
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#ifndef CONFIG_PARTITION_MODE
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static char vuart_rx_buf[RX_BUF_SIZE];
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static char vuart_tx_buf[TX_BUF_SIZE];
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#endif
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#define vuart_lock_init(vu) spinlock_init(&((vu)->lock))
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#define vuart_lock(vu) spinlock_obtain(&((vu)->lock))
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#define vuart_unlock(vu) spinlock_release(&((vu)->lock))
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#ifdef CONFIG_PARTITION_MODE
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uint16_t vuart_vmid = 0xFFFFU;
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#endif
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static inline void fifo_reset(struct fifo *fifo)
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{
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fifo->rindex = 0U;
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fifo->windex = 0U;
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fifo->num = 0U;
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}
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static inline void fifo_putchar(struct fifo *fifo, char ch)
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{
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fifo->buf[fifo->windex] = ch;
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if (fifo->num < fifo->size) {
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fifo->windex = (fifo->windex + 1U) % fifo->size;
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fifo->num++;
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} else {
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fifo->rindex = (fifo->rindex + 1U) % fifo->size;
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fifo->windex = (fifo->windex + 1U) % fifo->size;
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}
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}
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static inline char fifo_getchar(struct fifo *fifo)
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{
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char c;
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if (fifo->num > 0U) {
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c = fifo->buf[fifo->rindex];
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fifo->rindex = (fifo->rindex + 1U) % fifo->size;
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fifo->num--;
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return c;
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} else {
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return -1;
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}
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}
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static inline uint32_t fifo_numchars(const struct fifo *fifo)
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{
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return fifo->num;
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}
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static inline void vuart_fifo_init(struct acrn_vuart *vu)
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{
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#ifdef CONFIG_PARTITION_MODE
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vu->txfifo.buf = vu->vuart_tx_buf;
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vu->rxfifo.buf = vu->vuart_rx_buf;
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#else
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vu->txfifo.buf = vuart_tx_buf;
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vu->rxfifo.buf = vuart_rx_buf;
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#endif
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vu->txfifo.size = TX_BUF_SIZE;
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vu->rxfifo.size = RX_BUF_SIZE;
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fifo_reset(&(vu->txfifo));
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fifo_reset(&(vu->rxfifo));
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}
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/*
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* The IIR returns a prioritized interrupt reason:
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* - receive data available
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* - transmit holding register empty
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*
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* Return an interrupt reason if one is available.
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*/
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static uint8_t vuart_intr_reason(const struct acrn_vuart *vu)
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{
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if (((vu->lsr & LSR_OE) != 0U) && ((vu->ier & IER_ELSI) != 0U)) {
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return IIR_RLS;
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} else if ((fifo_numchars(&vu->rxfifo) > 0U) && ((vu->ier & IER_ERBFI) != 0U)) {
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return IIR_RXTOUT;
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} else if (vu->thre_int_pending && ((vu->ier & IER_ETBEI) != 0U)) {
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return IIR_TXRDY;
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} else {
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return IIR_NOPEND;
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}
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}
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struct acrn_vuart *vm_vuart(struct acrn_vm *vm)
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{
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return &(vm->vuart);
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}
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/*
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* Toggle the COM port's intr pin depending on whether or not we have an
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* interrupt condition to report to the processor.
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*/
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static void vuart_toggle_intr(const struct acrn_vuart *vu)
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{
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uint8_t intr_reason;
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union ioapic_rte rte;
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uint32_t operation;
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intr_reason = vuart_intr_reason(vu);
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vioapic_get_rte(vu->vm, vuart_com_irq, &rte);
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/* TODO:
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* Here should assert vuart irq according to CONFIG_COM_IRQ polarity.
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* The best way is to get the polarity info from ACIP table.
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* Here we just get the info from vioapic configuration.
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* based on this, we can still have irq storm during guest
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* modify the vioapic setting, as it's only for debug uart,
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* we want to make it as an known issue.
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*/
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if (rte.bits.intr_polarity == IOAPIC_RTE_INTPOL_ALO) {
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operation = (intr_reason != IIR_NOPEND) ? GSI_SET_LOW : GSI_SET_HIGH;
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} else {
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operation = (intr_reason != IIR_NOPEND) ? GSI_SET_HIGH : GSI_SET_LOW;
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}
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vpic_set_irqline(vu->vm, vuart_com_irq, operation);
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vioapic_set_irqline_lock(vu->vm, vuart_com_irq, operation);
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}
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static bool vuart_write(struct acrn_vm *vm, uint16_t offset_arg,
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__unused size_t width, uint32_t value)
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{
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uint16_t offset = offset_arg;
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struct acrn_vuart *vu = vm_vuart(vm);
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uint8_t value_u8 = (uint8_t)value;
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offset -= vu->base;
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vuart_lock(vu);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if ((vu->lcr & LCR_DLAB) != 0U) {
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if (offset == UART16550_DLL) {
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vu->dll = value_u8;
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goto done;
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}
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if (offset == UART16550_DLM) {
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vu->dlh = value_u8;
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goto done;
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}
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}
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switch (offset) {
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case UART16550_THR:
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fifo_putchar(&vu->txfifo, (char)value_u8);
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vu->thre_int_pending = true;
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break;
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case UART16550_IER:
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/*
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* Apply mask so that bits 4-7 are 0
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* Also enables bits 0-3 only if they're 1
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*/
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vu->ier = value_u8 & 0x0FU;
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break;
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case UART16550_FCR:
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/*
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* The FCR_ENABLE bit must be '1' for the programming
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* of other FCR bits to be effective.
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*/
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if ((value_u8 & FCR_FIFOE) == 0U) {
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vu->fcr = 0U;
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} else {
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if ((value_u8 & FCR_RFR) != 0U) {
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fifo_reset(&vu->rxfifo);
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}
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vu->fcr = value_u8 & (FCR_FIFOE | FCR_DMA | FCR_RX_MASK);
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}
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break;
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case UART16550_LCR:
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vu->lcr = value_u8;
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break;
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case UART16550_MCR:
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/* ignore modem */
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break;
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case UART16550_LSR:
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/*
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* Line status register is not meant to be written to
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* during normal operation.
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*/
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break;
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case UART16550_MSR:
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/*
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* As far as I can tell MSR is a read-only register.
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*/
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break;
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case UART16550_SCR:
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vu->scr = value_u8;
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break;
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default:
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/*
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* For the offset that is not handled (either a read-only
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* register or an invalid register), ignore the write to it.
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* Gracefully return if prior case clauses have not been met.
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*/
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break;
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}
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done:
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vuart_toggle_intr(vu);
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vuart_unlock(vu);
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return true;
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}
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static bool vuart_read(struct acrn_vm *vm, struct acrn_vcpu *vcpu, uint16_t offset_arg,
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__unused size_t width)
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{
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uint16_t offset = offset_arg;
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uint8_t iir, reg, intr_reason;
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struct acrn_vuart *vu = vm_vuart(vm);
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struct pio_request *pio_req = &vcpu->req.reqs.pio;
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offset -= vu->base;
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vuart_lock(vu);
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/*
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* Take care of the special case DLAB accesses first
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*/
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if ((vu->lcr & LCR_DLAB) != 0U) {
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if (offset == UART16550_DLL) {
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reg = vu->dll;
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goto done;
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}
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if (offset == UART16550_DLM) {
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reg = vu->dlh;
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goto done;
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}
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}
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switch (offset) {
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case UART16550_RBR:
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vu->lsr &= ~LSR_OE;
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reg = (uint8_t)fifo_getchar(&vu->rxfifo);
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break;
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case UART16550_IER:
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reg = vu->ier;
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break;
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case UART16550_IIR:
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iir = ((vu->fcr & FCR_FIFOE) != 0U) ? IIR_FIFO_MASK : 0U;
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intr_reason = vuart_intr_reason(vu);
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/*
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* Deal with side effects of reading the IIR register
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*/
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if (intr_reason == IIR_TXRDY) {
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vu->thre_int_pending = false;
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}
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iir |= intr_reason;
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reg = iir;
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break;
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case UART16550_LCR:
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reg = vu->lcr;
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break;
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case UART16550_MCR:
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reg = vu->mcr;
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break;
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case UART16550_LSR:
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/* Transmitter is always ready for more data */
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vu->lsr |= LSR_TEMT | LSR_THRE;
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/* Check for new receive data */
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if (fifo_numchars(&vu->rxfifo) > 0U) {
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vu->lsr |= LSR_DR;
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} else {
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vu->lsr &= ~LSR_DR;
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}
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reg = vu->lsr;
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/* The LSR_OE bit is cleared on LSR read */
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vu->lsr &= ~LSR_OE;
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break;
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case UART16550_MSR:
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/* ignore modem I*/
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reg = 0U;
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break;
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case UART16550_SCR:
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reg = vu->scr;
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break;
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default:
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reg = 0xFFU;
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break;
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}
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done:
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vuart_toggle_intr(vu);
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pio_req->value = (uint32_t)reg;
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vuart_unlock(vu);
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return true;
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}
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static void vuart_register_io_handler(struct acrn_vm *vm)
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{
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struct vm_io_range range = {
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.flags = IO_ATTR_RW,
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.base = vuart_com_base,
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.len = 8U
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};
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register_pio_emulation_handler(vm, UART_PIO_IDX, &range, vuart_read, vuart_write);
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}
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/**
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* @pre vu != NULL
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*/
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void vuart_console_tx_chars(struct acrn_vuart *vu)
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{
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vuart_lock(vu);
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while (fifo_numchars(&vu->txfifo) > 0U) {
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printf("%c", fifo_getchar(&vu->txfifo));
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}
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vuart_unlock(vu);
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}
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/**
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* @pre vu != NULL
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* @pre vu->active == true
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*/
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void vuart_console_rx_chars(struct acrn_vuart *vu)
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{
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char ch = -1;
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vuart_lock(vu);
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/* Get data from physical uart */
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ch = uart16550_getc();
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if (ch == GUEST_CONSOLE_TO_HV_SWITCH_KEY) {
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/* Switch the console */
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vu->active = false;
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printf("\r\n\r\n ---Entering ACRN SHELL---\r\n");
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}
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if (ch != -1) {
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fifo_putchar(&vu->rxfifo, ch);
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vuart_toggle_intr(vu);
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}
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vuart_unlock(vu);
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}
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struct acrn_vuart *vuart_console_active(void)
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{
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struct acrn_vm *vm = NULL;
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#ifdef CONFIG_PARTITION_MODE
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if (vuart_vmid < CONFIG_MAX_VM_NUM) {
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vm = get_vm_from_vmid(vuart_vmid);
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}
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#else
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vm = get_sos_vm();
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#endif
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if (is_valid_vm(vm)) {
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struct acrn_vuart *vu = vm_vuart(vm);
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if (vu->active) {
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return vu;
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}
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}
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return NULL;
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}
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void vuart_init(struct acrn_vm *vm)
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{
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uint32_t divisor;
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struct acrn_vuart *vu = vm_vuart(vm);
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/* Set baud rate*/
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divisor = (UART_CLOCK_RATE / BAUD_9600) >> 4U;
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vm->vuart.dll = (uint8_t)divisor;
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vm->vuart.dlh = (uint8_t)(divisor >> 8U);
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vm->vuart.active = false;
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vm->vuart.base = vuart_com_base;
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vm->vuart.vm = vm;
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vuart_fifo_init(vu);
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vuart_lock_init(vu);
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vuart_register_io_handler(vm);
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}
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bool hv_used_dbg_intx(uint32_t intx_pin)
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{
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return is_dbg_uart_enabled() && (intx_pin == vuart_com_irq);
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}
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/* vuart=ttySx@irqN, like vuart=ttyS1@irq6 head "vuart=ttyS" is parsed */
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void vuart_set_property(const char *vuart_info)
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{
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const uint16_t com_map[4] = {0x3f8, 0x2F8, 0x3E8, 0x2E8}; /* map to ttyS0-ttyS3 */
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uint8_t com_idx;
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com_idx = (uint8_t)(vuart_info[0] - '0');
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if (com_idx < 4) {
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vuart_com_base = com_map[com_idx];
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}
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if (strncmp(vuart_info + 1, "@irq", 4) == 0) {
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vuart_com_irq = (uint8_t)strtol_deci(vuart_info + 5);
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}
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}
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