155 lines
3.9 KiB
C
155 lines
3.9 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PTDEV_H
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#define PTDEV_H
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#include <list.h>
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#include <spinlock.h>
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#include <timer.h>
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#define PTDEV_INTR_MSI (1U << 0U)
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#define PTDEV_INTR_INTX (1U << 1U)
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#define INVALID_PTDEV_ENTRY_ID 0xffffU
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#define PTDEV_VPIN_IOAPIC 0x0U
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#define PTDEV_VPIN_PIC 0x1U
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#define DEFINE_MSI_SID(name, a, b) \
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union source_id (name) = {.msi_id = {.bdf = (a), .entry_nr = (b)} }
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#define DEFINE_IOAPIC_SID(name, a, b) \
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union source_id (name) = {.intx_id = {.pin = (a), .src = (b)} }
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union irte_index {
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uint16_t index;
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struct {
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uint16_t index_low:15;
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uint16_t index_high:1;
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} bits __packed;
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};
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union source_id {
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uint64_t value;
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struct {
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uint16_t bdf;
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uint16_t entry_nr;
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uint32_t reserved;
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} msi_id;
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struct {
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uint32_t pin;
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uint32_t src;
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} intx_id;
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};
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/*
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* Macros for bits in union msi_addr_reg
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*/
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#define MSI_ADDR_BASE 0xfeeUL /* Base address for MSI messages */
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#define MSI_ADDR_RH 0x1U /* Redirection Hint */
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#define MSI_ADDR_DESTMODE_LOGICAL 0x1U /* Destination Mode: Logical*/
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#define MSI_ADDR_DESTMODE_PHYS 0x0U /* Destination Mode: Physical*/
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union msi_addr_reg {
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uint64_t full;
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struct {
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uint32_t rsvd_1:2;
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uint32_t dest_mode:1;
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uint32_t rh:1;
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uint32_t rsvd_2:8;
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uint32_t dest_field:8;
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uint32_t addr_base:12;
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uint32_t hi_32;
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} bits __packed;
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struct {
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uint32_t rsvd_1:2;
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uint32_t intr_index_high:1;
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uint32_t shv:1;
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uint32_t intr_format:1;
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uint32_t intr_index_low:15;
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uint32_t constant:12;
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uint32_t hi_32;
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} ir_bits __packed;
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};
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/*
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* Macros for bits in union msi_data_reg
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*/
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#define MSI_DATA_DELMODE_FIXED 0x0U /* Delivery Mode: Fixed */
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#define MSI_DATA_DELMODE_LOPRI 0x1U /* Delivery Mode: Low Priority */
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#define MSI_DATA_TRGRMODE_EDGE 0x0U /* Trigger Mode: Edge */
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#define MSI_DATA_TRGRMODE_LEVEL 0x1U /* Trigger Mode: Level */
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union msi_data_reg {
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uint32_t full;
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struct {
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uint32_t vector:8;
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uint32_t delivery_mode:3;
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uint32_t rsvd_1:3;
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uint32_t level:1;
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uint32_t trigger_mode:1;
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uint32_t rsvd_2:16;
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} bits __packed;
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};
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/* entry per guest virt vector */
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struct ptirq_msi_info {
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union msi_addr_reg vmsi_addr; /* virt msi_addr */
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union msi_data_reg vmsi_data; /* virt msi_data */
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union msi_addr_reg pmsi_addr; /* phys msi_addr */
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union msi_data_reg pmsi_data; /* phys msi_data */
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};
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struct ptirq_remapping_info;
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typedef void (*ptirq_arch_release_fn_t)(const struct ptirq_remapping_info *entry);
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/* entry per each allocated irq/vector
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* it represents a pass-thru device's remapping data entry which collecting
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* information related with its vm and msi/intx mapping & interaction nodes
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* with interrupt handler and softirq.
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*/
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struct ptirq_remapping_info {
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uint16_t ptdev_entry_id;
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uint32_t intr_type;
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union source_id phys_sid;
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union source_id virt_sid;
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struct acrn_vm *vm;
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bool active; /* true=active, false=inactive*/
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uint32_t allocated_pirq;
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uint32_t polarity; /* 0=active high, 1=active low*/
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struct list_head softirq_node;
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struct ptirq_msi_info msi;
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uint64_t intr_count;
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struct hv_timer intr_delay_timer; /* used for delay intr injection */
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ptirq_arch_release_fn_t release_cb;
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};
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static inline bool is_entry_active(const struct ptirq_remapping_info *entry)
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{
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return entry->active;
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}
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extern struct ptirq_remapping_info ptirq_entries[CONFIG_MAX_PT_IRQ_ENTRIES];
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extern spinlock_t ptdev_lock;
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void ptirq_softirq(uint16_t pcpu_id);
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void ptdev_init(void);
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void ptdev_release_all_entries(const struct acrn_vm *vm);
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struct ptirq_remapping_info *ptirq_dequeue_softirq(uint16_t pcpu_id);
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struct ptirq_remapping_info *ptirq_alloc_entry(struct acrn_vm *vm, uint32_t intr_type);
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void ptirq_release_entry(struct ptirq_remapping_info *entry);
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int32_t ptirq_activate_entry(struct ptirq_remapping_info *entry, uint32_t phys_irq);
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void ptirq_deactivate_entry(struct ptirq_remapping_info *entry);
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uint32_t ptirq_get_intr_data(const struct acrn_vm *target_vm, uint64_t *buffer, uint32_t buffer_cnt);
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#endif /* PTDEV_H */
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