201 lines
4.4 KiB
C
201 lines
4.4 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/**
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* @file mmu.h
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*
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* @brief APIs for Memory Management module
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*/
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#ifndef MMU_H
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#define MMU_H
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/**
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* @brief Memory Management
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*
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* @defgroup acrn_mem ACRN Memory Management
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* @{
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*/
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/** The flag that indicates that the page fault was caused by a non present
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* page.
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*/
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#define PAGE_FAULT_P_FLAG 0x00000001U
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/** The flag that indicates that the page fault was caused by a write access. */
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#define PAGE_FAULT_WR_FLAG 0x00000002U
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/** The flag that indicates that the page fault was caused in user mode. */
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#define PAGE_FAULT_US_FLAG 0x00000004U
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/** The flag that indicates that the page fault was caused by a reserved bit
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* violation.
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*/
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#define PAGE_FAULT_RSVD_FLAG 0x00000008U
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/** The flag that indicates that the page fault was caused by an instruction
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* fetch.
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*/
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#define PAGE_FAULT_ID_FLAG 0x00000010U
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/* Defines used for common memory sizes */
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#define MEM_1K 1024U
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#define MEM_2K (MEM_1K * 2U)
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#define MEM_4K (MEM_1K * 4U)
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#define MEM_1M (MEM_1K * 1024U)
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#define MEM_2M (MEM_1M * 2U)
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#define MEM_1G (MEM_1M * 1024U)
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#ifndef ASSEMBLER
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#include <cpu.h>
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#include <page.h>
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#include <pgtable.h>
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#include <cpu_caps.h>
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/* Define cache line size (in bytes) */
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#define CACHE_LINE_SIZE 64U
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/* IA32E Paging constants */
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#define IA32E_REF_MASK ((get_pcpu_info())->physical_address_mask)
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struct acrn_vcpu;
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static inline uint64_t round_page_up(uint64_t addr)
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{
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return (((addr + (uint64_t)PAGE_SIZE) - 1UL) & PAGE_MASK);
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}
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static inline uint64_t round_page_down(uint64_t addr)
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{
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return (addr & PAGE_MASK);
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}
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static inline uint64_t round_pde_up(uint64_t val)
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{
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return (((val + (uint64_t)PDE_SIZE) - 1UL) & PDE_MASK);
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}
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static inline uint64_t round_pde_down(uint64_t val)
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{
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return (val & PDE_MASK);
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}
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/**
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* @brief Page tables level in IA32 paging mode
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*/
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enum _page_table_level {
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/**
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* @brief The PML4 level in the page tables
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*/
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IA32E_PML4 = 0,
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/**
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* @brief The Page-Directory-Pointer-Table level in the page tables
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*/
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IA32E_PDPT = 1,
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/**
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* @brief The Page-Directory level in the page tables
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*/
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IA32E_PD = 2,
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/**
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* @brief The Page-Table level in the page tables
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*/
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IA32E_PT = 3,
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};
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/* Page size */
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#define PAGE_SIZE_4K MEM_4K
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#define PAGE_SIZE_2M MEM_2M
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#define PAGE_SIZE_1G MEM_1G
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void sanitize_pte_entry(uint64_t *ptep, const struct memory_ops *mem_ops);
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void sanitize_pte(uint64_t *pt_page, const struct memory_ops *mem_ops);
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/**
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* @brief MMU paging enable
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*
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* @return None
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*/
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void enable_paging(void);
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/**
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* @brief Supervisor-mode execution prevention (SMEP) enable
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*
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* @return None
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*/
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void enable_smep(void);
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/**
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* @brief Supervisor-mode Access Prevention (SMAP) enable
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*
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* @return None
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*/
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void enable_smap(void);
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/**
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* @brief MMU page tables initialization
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*
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* @return None
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*/
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void init_paging(void);
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void mmu_add(uint64_t *pml4_page, uint64_t paddr_base, uint64_t vaddr_base,
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uint64_t size, uint64_t prot, const struct memory_ops *mem_ops);
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void mmu_modify_or_del(uint64_t *pml4_page, uint64_t vaddr_base, uint64_t size,
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uint64_t prot_set, uint64_t prot_clr, const struct memory_ops *mem_ops, uint32_t type);
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void hv_access_memory_region_update(uint64_t base, uint64_t size);
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/**
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* @brief Specified signle VPID flush
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*
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* @param[in] vpid the specified VPID
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*
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* @return None
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*/
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void flush_vpid_single(uint16_t vpid);
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/**
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* @brief All VPID flush
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*
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* @return None
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*/
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void flush_vpid_global(void);
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/**
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* @brief Flush address space
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*
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* @param[in] addr the specified virtual address
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*
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* @param[in] size the specified size to flush
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*
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* @return None
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*/
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void flush_address_space(void *addr, uint64_t size);
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/**
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* @brief Guest-physical mappings and combined mappings invalidation
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*
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* @param[in] eptp the pointer that points the eptp
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*
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* @return None
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*/
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void invept(const void *eptp);
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static inline void cache_flush_invalidate_all(void)
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{
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asm volatile (" wbinvd\n" : : : "memory");
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}
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static inline void clflush(const volatile void *p)
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{
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asm volatile ("clflush (%0)" :: "r"(p));
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}
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static inline void clflushopt(const volatile void *p)
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{
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asm volatile ("clflushopt (%0)" :: "r"(p));
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}
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/* get PDPT address from CR3 vaule in PAE mode */
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static inline uint64_t get_pae_pdpt_addr(uint64_t cr3)
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{
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return (cr3 & 0xFFFFFFE0UL);
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}
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/**
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* @}
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*/
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#endif /* ASSEMBLER not defined */
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#endif /* MMU_H */
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