296 lines
7.0 KiB
C
296 lines
7.0 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <asm/lib/spinlock.h>
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#include <pci.h>
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#include <uart16550.h>
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#include <asm/io.h>
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#include <asm/cpu.h>
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#include <asm/mmu.h>
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#define MAX_BDF_LEN 8
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struct console_uart {
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bool enabled;
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enum serial_dev_type type;
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uint16_t port_address;
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void *mmio_base_vaddr;
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union pci_bdf bdf;
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spinlock_t rx_lock;
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spinlock_t tx_lock;
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uint32_t reg_width;
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};
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#if defined(CONFIG_SERIAL_PIO_BASE)
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static struct console_uart uart = {
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.enabled = true,
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.type = PIO,
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.port_address = CONFIG_SERIAL_PIO_BASE,
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.reg_width = 1,
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};
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#elif defined(CONFIG_SERIAL_PCI_BDF)
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static struct console_uart uart = {
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.enabled = true,
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.type = PCI,
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.bdf.value = CONFIG_SERIAL_PCI_BDF,
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.reg_width = 4,
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};
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#elif defined(CONFIG_SERIAL_MMIO_BASE)
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static struct console_uart uart = {
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.enabled = true,
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.type = MMIO,
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.mmio_base_vaddr = (void *)CONFIG_SERIAL_MMIO_BASE,
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.reg_width = 1,
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};
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#endif
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typedef uint32_t uart_reg_t;
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/**
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* @pre uart->enabled == true
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*/
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static inline uint32_t uart16550_read_reg(struct console_uart uart, uint16_t reg_idx)
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{
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if (uart.type == PIO) {
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return pio_read8(uart.port_address + (reg_idx * uart.reg_width));
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} else {
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if (uart.reg_width == 4U) {
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return mmio_read32(uart.mmio_base_vaddr + (reg_idx * uart.reg_width));
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} else {
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return mmio_read8(uart.mmio_base_vaddr + (reg_idx * uart.reg_width));
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}
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}
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}
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/**
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* @pre uart->enabled == true
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*/
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static inline void uart16550_write_reg(struct console_uart uart, uint32_t val, uint16_t reg_idx)
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{
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if (uart.type == PIO) {
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pio_write8(val, uart.port_address + (reg_idx * uart.reg_width));
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} else {
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if (uart.reg_width == 4U) {
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mmio_write32(val, uart.mmio_base_vaddr + (reg_idx * uart.reg_width));
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} else {
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mmio_write8(val, uart.mmio_base_vaddr + (reg_idx * uart.reg_width));
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}
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}
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}
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static void uart16550_calc_baud_div(uint32_t ref_freq, uint32_t *baud_div_ptr, uint32_t baud_rate_arg)
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{
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uint32_t baud_rate = baud_rate_arg;
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uint32_t baud_multiplier = baud_rate < BAUD_460800 ? 16U : 13U;
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if (baud_rate == 0U) {
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baud_rate = BAUD_115200;
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}
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*baud_div_ptr = ref_freq / (baud_multiplier * baud_rate);
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}
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/**
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* @pre uart->enabled == true
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*/
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static void uart16550_set_baud_rate(uint32_t baud_rate)
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{
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uint32_t baud_div, duart_clock = UART_CLOCK_RATE;
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uart_reg_t temp_reg;
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/* Calculate baud divisor */
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uart16550_calc_baud_div(duart_clock, &baud_div, baud_rate);
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/* Enable DLL and DLM registers for setting the Divisor */
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temp_reg = uart16550_read_reg(uart, UART16550_LCR);
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temp_reg |= LCR_DLAB;
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uart16550_write_reg(uart, temp_reg, UART16550_LCR);
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/* Write the appropriate divisor value */
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uart16550_write_reg(uart, ((baud_div >> 8U) & 0xFFU), UART16550_DLM);
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uart16550_write_reg(uart, (baud_div & 0xFFU), UART16550_DLL);
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/* Disable DLL and DLM registers */
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temp_reg &= ~LCR_DLAB;
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uart16550_write_reg(uart, temp_reg, UART16550_LCR);
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}
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void uart16550_init(bool early_boot)
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{
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void *mmio_base_va = NULL;
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if (!uart.enabled) {
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return;
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}
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if (!early_boot) {
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if (uart.type == MMIO) {
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mmio_base_va = hpa2hva(hva2hpa_early(uart.mmio_base_vaddr));
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if (mmio_base_va != NULL) {
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set_paging_supervisor((uint64_t)mmio_base_va, PDE_SIZE);
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}
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}
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return;
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}
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/* if configure serial PCI BDF, get its base MMIO address */
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if (uart.type == PCI) {
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uint32_t bar0 = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(0), 4U);
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if ((bar0 & ~0xfU) == 0U) {
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/* in case the PCI UART BAR is reset to 0 after boot */
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uart.enabled = false;
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return;
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} else {
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uint16_t cmd = (uint16_t)pci_pdev_read_cfg(uart.bdf, PCIR_COMMAND, 2U);
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if ((bar0 & 0x3U) == PCIM_BAR_IO_SPACE) { /* IO Space */
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uart.type = PIO;
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uart.port_address = (uint16_t)(bar0 & PCI_BASE_ADDRESS_IO_MASK);
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uart.reg_width = 1;
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pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_PORTEN);
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} else {
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uint32_t bar_hi = pci_pdev_read_cfg(uart.bdf, pci_bar_offset(1), 4U);
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/* Enable the PCI UART if the BAR is 32bit, or 64bit with 4GB- mmio space. */
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if (((bar0 & 0x7U) == 0U) || (((bar0 & 0x7U) == 4U) && (bar_hi == 0U))) {
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uart.type = MMIO;
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uart.mmio_base_vaddr = hpa2hva_early((bar0 & PCI_BASE_ADDRESS_MEM_MASK));
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pci_pdev_write_cfg(uart.bdf, PCIR_COMMAND, 2U, cmd | PCIM_CMD_MEMEN);
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} else {
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/* TODO: enable 64bit BAR with 4GB+ mmio space */
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uart.enabled = false;
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return;
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}
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}
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}
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}
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spinlock_init(&uart.rx_lock);
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spinlock_init(&uart.tx_lock);
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/* Enable TX and RX FIFOs */
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uart16550_write_reg(uart, FCR_FIFOE | FCR_RFR | FCR_TFR, UART16550_FCR);
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/* Set-up data bits / parity / stop bits. */
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uart16550_write_reg(uart, (LCR_WL8 | LCR_NB_STOP_BITS_1 | LCR_PARITY_NONE), UART16550_LCR);
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/* Disable interrupts (we use polling) */
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uart16550_write_reg(uart, UART_IER_DISABLE_ALL, UART16550_IER);
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/* Set baud rate */
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uart16550_set_baud_rate(BAUD_115200);
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/* Data terminal ready + Request to send */
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uart16550_write_reg(uart, MCR_RTS | MCR_DTR, UART16550_MCR);
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}
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char uart16550_getc(void)
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{
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char ret = -1;
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uint64_t rflags;
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if (!uart.enabled) {
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return ret;
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}
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spinlock_irqsave_obtain(&uart.rx_lock, &rflags);
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/* If a character has been received, read it */
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if ((uart16550_read_reg(uart, UART16550_LSR) & LSR_DR) == LSR_DR) {
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/* Read a character */
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ret = uart16550_read_reg(uart, UART16550_RBR);
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}
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spinlock_irqrestore_release(&uart.rx_lock, rflags);
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return ret;
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}
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/**
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* @pre uart->enabled == true
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*/
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static void uart16550_putc(char c)
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{
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uint8_t temp;
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uint32_t reg;
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/* Ensure there are no further Transmit buffer write requests */
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do {
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reg = uart16550_read_reg(uart, UART16550_LSR);
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} while ((reg & LSR_THRE) == 0U || (reg & LSR_TEMT) == 0U);
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temp = (uint8_t)c;
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/* Transmit the character. */
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uart16550_write_reg(uart, (uint32_t)temp, UART16550_THR);
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}
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size_t uart16550_puts(const char *buf, uint32_t len)
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{
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uint32_t i;
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uint64_t rflags;
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if (!uart.enabled) {
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return len;
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}
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spinlock_irqsave_obtain(&uart.tx_lock, &rflags);
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for (i = 0U; i < len; i++) {
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/* Transmit character */
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uart16550_putc(*buf);
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if (*buf == '\n') {
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/* Append '\r', no need change the len */
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uart16550_putc('\r');
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}
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buf++;
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}
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spinlock_irqrestore_release(&uart.tx_lock, rflags);
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return len;
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}
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void uart16550_set_property(bool enabled, enum serial_dev_type uart_type, uint64_t data)
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{
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uart.enabled = enabled;
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uart.type = uart_type;
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uart.bdf.value = 0U;
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if (uart_type == PIO) {
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uart.port_address = data;
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} else if (uart_type == PCI) {
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uart.bdf.value = data;
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uart.reg_width = 4;
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} else if (uart_type == MMIO) {
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uart.mmio_base_vaddr = (void *)data;
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uart.reg_width = 1;
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}
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}
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bool is_pci_dbg_uart(union pci_bdf bdf_value)
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{
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bool ret = false;
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if (uart.enabled && (uart.bdf.value != 0)) {
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if (bdf_value.value == uart.bdf.value) {
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ret = true;
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}
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}
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return ret;
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}
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bool get_pio_dbg_uart_cfg(uint16_t *pio_address, uint32_t *nbytes)
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{
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bool ret = false;
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if (uart.enabled && (uart.type == PIO)) {
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*pio_address = uart.port_address;
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*nbytes = 8U;
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ret = true;
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}
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return ret;
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}
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