161 lines
4.2 KiB
C
161 lines
4.2 KiB
C
/*-
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <string.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "vmmapi.h"
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#include "sw_load.h"
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#include "dm.h"
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int with_bootargs;
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static char bootargs[STR_LEN];
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/*
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* Default e820 mem map:
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*
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* there is reserved memory hole for PCI hole and APIC etc
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* so the memory layout could be separated into lowmem & highmem.
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* - if request memory size <= ctx->lowmem_limit, then there is only
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* map[0]:0~ctx->lowmem for RAM
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* ctx->lowmem = request_memory_size
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* - if request memory size > ctx->lowmem_limit, then there are
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* map[0]:0~ctx->lowmem_limit & map[2]:4G~ctx->highmem for RAM
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* ctx->highmem = request_memory_size - ctx->lowmem_limit
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*
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* Begin End Type Length
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* 0: 0 - lowmem RAM lowmem
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* 1: lowmem - bff_fffff (reserved) 0xc00_00000-lowmem
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* 2: 0xc00_00000 - dff_fffff PCI hole 512MB
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* 3: 0xe00_00000 - fff_fffff (reserved) 512MB
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* 2: 1_000_00000 - highmem RAM highmem-4G
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*/
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const struct e820_entry e820_default_entries[NUM_E820_ENTRIES] = {
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{ /* 0 to lowmem */
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.baseaddr = 0x00000000,
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.length = 0x49000000,
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.type = E820_TYPE_RAM
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},
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{ /* lowmem to lowmem_limit*/
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.baseaddr = 0x49000000,
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.length = 0x77000000,
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.type = E820_TYPE_RESERVED
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},
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{ /* lowmem_limit to 4G */
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.baseaddr = 0xe0000000,
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.length = 0x20000000,
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.type = E820_TYPE_RESERVED
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},
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{
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.baseaddr = 0x100000000,
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.length = 0x000100000,
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.type = E820_TYPE_RESERVED
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},
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};
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int
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acrn_parse_bootargs(char *arg)
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{
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int len = strlen(arg);
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if (len < STR_LEN) {
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strncpy(bootargs, arg, len);
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bootargs[len] = '\0';
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with_bootargs = 1;
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printf("SW_LOAD: get bootargs %s\n", bootargs);
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return 0;
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} else
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return -1;
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}
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char*
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get_bootargs(void)
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{
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return bootargs;
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}
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int
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check_image(char *path)
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{
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FILE *fp;
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fp = fopen(path, "r");
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if (fp == NULL)
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return -1;
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fclose(fp);
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return 0;
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}
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uint32_t
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acrn_create_e820_table(struct vmctx *ctx, struct e820_entry *e820)
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{
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uint32_t k;
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memcpy(e820, e820_default_entries, sizeof(e820_default_entries));
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if (ctx->lowmem > 0) {
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e820[LOWRAM_E820_ENTRIES].length = ctx->lowmem;
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e820[LOWRAM_E820_ENTRIES+1].baseaddr = ctx->lowmem;
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e820[LOWRAM_E820_ENTRIES+1].length =
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ctx->lowmem_limit - ctx->lowmem;
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}
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if (ctx->highmem > 0) {
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e820[HIGHRAM_E820_ENTRIES].type = E820_TYPE_RAM;
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e820[HIGHRAM_E820_ENTRIES].length = ctx->highmem;
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}
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printf("SW_LOAD: build e820 %d entries to addr: %p\n",
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NUM_E820_ENTRIES, (void *)e820);
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for (k = 0; k < NUM_E820_ENTRIES; k++)
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printf("SW_LOAD: entry[%d]: addr 0x%016lx, size 0x%016lx, "
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" type 0x%x\n",
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k, e820[k].baseaddr,
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e820[k].length,
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e820[k].type);
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return NUM_E820_ENTRIES;
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}
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int
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acrn_sw_load(struct vmctx *ctx)
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{
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if (vsbl_file_name)
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return acrn_sw_load_vsbl(ctx);
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else
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return acrn_sw_load_bzimage(ctx);
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}
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